BIOS and DOS Interrupts Basic Input /Outpu System Disk Operating System

Computer Interrupt Interrupt request : a signal that immediate attention is needed Interrupt processing: what CPU does in response to request Interrupt service: what is done in software as a result

Computer Interrupt 2 General Types of Interrupts: External - generated outside CPU by other hardware Internal - generated within CPU as a result of instruction or operation - x86 internals: int, into, divide error, and single step - “trap” generally means any processor generated interrupt; in x86, usually means the single step interrupt x86 Terminology for Interrupts: 1) Hardware Interrupt – External, uses INTR and NMI control bus lines 2) Software Interrupt – Internal, from int or into 3) Processor Interrupt – traps, exceptions

8086/8088 Pinout Diagrams

8086 External Interrupt Connections NMI - Non-Maskable InterruptINTR - Interrupt Request Interrupt Logic int into Divide Error Single Step NMI Requesting Device 8086 CPU Intel 8259A PIC NMI INTR SoftwareTraps Programmable Interrupt Controller (part of chipset)

Interrupt Vector Table – IVT (in memory) x86 has 256 interrupts, specified by Type Number or Vector 1 byte of data must accompany each interrupt; specifies Type Vector is a pointer (address) into Interrupt Vector Table, IVT –IVT is stored in memory from 0000:0000 to 0000:03ffh IVT contains 256 far pointer values (addresses) –Far pointer is CS:IP values Each far pointer is address of Interrupt Service Routine, ISR –Also referred to as Interrupt Handler When interrupt is requested, which IVT entry? Type!

IVT Format Offset Segment Interrupt 0 Interrupt 1 Interrupt : : : : : : : : :03fc 0000:03fd 0000:03fe 0000:03ff IP LSB IP MSB CS LSB CS MSB Given a Vector, where is the ISR address stored in memory ? Example: int 36h Offset = (54  4) = 216 = 00d8h

What Happens During an Interrupt ? Complete Current Instruction Internal Interrupt NMI INTR TF Fetch Next Instruction IF Read Type Code # push Flags Set TEMP=TF IF=0 TF=0 push CS and IP call ISR NMI TF=TEMP pop IP and CS popf Resume Interrupted Procedure YES NO acknowledge interrupt

Similarity to Subroutine Procedure call  int ret  iret call pushes CS, IP and loads CS:IP with address of subroutine int does what call does and more ret pops IP, CS iret pops FLAGS, IP, and CS This is why ALL programs MUST have a stack segment, so that interrupts can be handled

halt Instruction This instruction causes processor to enter a HALT state HALT state is one where no further instructions are fetched nor executed until one of the following events occurs: 1) System is reset - rising edge on RESET pin 2) External interrupt occurs

Interrupt Vector Assignments

Interrupt Vector Assignments (cont.)

AT – IRQ Definitions IBM-AT (Advanced Technology) - Intel 80286

Interrupt Service Routines ALL Interrupts Interrupts for Inpu Interrupts for Output

Interrupts for Inpu INT 16h / AH = 00h - get keystroke from keyboard (no echo) INT 16h / AH = 00h INT 16h / AH = 01h - check for keystroke in the keyboard buffer INT 16h / AH = 01h INT 21h / AH=1 - read character from standard input, with echo INT 21h / AH=1 INT 21h / AH=6 - direct console input or output INT 21h / AH=6 INT 21h / AH=7 - character input without echo to AL INT 21h / AH=7 INT 21h / AH=0Ah - input of a string INT 21h / AH=0Ah INT 21h / AH=0Bh - get input status INT 21h / AH=0Bh

Interrupts for Output INT 21h / AH=2 - write character to standard output INT 21h / AH=2 INT 21h / AH=9 - output of a string INT 21h / AH=9

HW#1 Develop an assembly program that receives a decimal number (up to max 100 digits) from user and displays its hexadecimal equivallent. Due Date: Sunday Esfand 23 rd Mail to: Mr Kazari and me or Subject: HW1 UPI2010 IDxxxxxxxx