The 8051 Microcontroller Chapter 6 INTERRUPTS

2/29 Interrupt is the occurrence of a condition an event that causes a temporary suspension of a program while the condition is a serviced by another program An interrupt-driven system gives illusion of doing many things simultaneosly The CPU can execute only one instruction at a time The program that deals with an interrupt is Interrupt Service routine ISR

3/29 Base-level ( foreground ) Interrupt level ( background )

4/29 Interrupt organization On the 8051, 5 interrupt sources, two external, two timer and a serial port interrupt The 8052 adds a sixth interrupt source form the extra timer

5/29 Each of the interrupt sources is individually enabled or disabled through the bit-addressable register Interrupt Enable IE Global enable/disable bit to enable/disable all interrupts

6/29 Interrupt priority Each interrupt source is individually programmed to one of two priority levels through the bit-addressable special function register Interrupt Priority IP at address 0B8H IP is cleared after a system reset to place all interrupts at the lower priority level by default

7/29 Polling sequence If two interrupts of the same priority occur simultaneosly, a fixed polling sequence determines which is serviced first The polling sequence is external 0, Timer 0, external 1, Timer 1, serial port, Timer 2

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9/29 Processing interrupts When an interrupt occurs and is accepted by the CPU, the main program is interrapted, then: The cuurent instruction completes execution The PC is saved on the stack The current interrupt status is saved internally Interrupts are blocked at the level of the interrupt The PC is loaded with the vector address of the ISR The ISR executes

10/29 Interrupt Vectors When the interrupt is accepted, the value loaded into the PC is called interrupt vector It is the address of the start of the ISR for the interrupting source The system reset vector RST is at address 0000H

11/29 Program design using interrupts The first instruction jumps to address 0030H, just the above the vector locations where the ISRs begins The main program begins at address 0030H

12/29 Small interrupt Service Routines Interrupt service routines must begin near the bottom of code memory at the addresses shown in table 6-4

13/29 Large Interrupt Service Routines If the ISR is longer than 8 bytes, in may be necessary to move it elsewhere in code memory Tipically the ISR begins with a jump to another area of code memory where the ISR can strech out

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17/29 Serial Port Interrupts Serial Port occurs when either the T1 or R1 is set The flag is not cleared by hardware when the COU vectors to the interrupt, because there are two sources for interrupt T1 or R1 The source of the interrupt must be determined in the ISR and interrupting flag cleared by software

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20/29 External Interrupts External interrupts occur as a result of a low-level or negative edge on the INT0 or INT1 pin on the 8051 IC

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27/29 Interrupt Timings Interrupts are sampled and latched on S5P2 of each machine cycle, it is accepted if : a) no other interrupt of equal or higher priority is in progress b) the polling cycle is the last cycle in an instruction c) the cuurent instruction is not a RET1 or any access to IE or IP

28/29 The stipulation that the cuurent instruction is not R1 ensures that at least one instrucion executes after each interrupt service routine Interrupt latency

29/29 Summary Users can develop self-contained interrupt applications The object can be burned into EPROM and installed in the target system at code address 0000h, when the system is powered on or reset the application begins execution without program for loading and starting the application