1. UNIT 5 TIMRERS/COUNTERS
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2. One “machine cycle” = 6 states (S1 - S6) One state = 2 clock cycles
Instruction Timing
One “machine cycle” = 6 states (S1 - S6)
One state = 2 clock cycles
One “machine cycle” = 12 clock cycles
Instructions take cycles
e.g. 1 cycle instructions: ADD, MOV, SETB, NOP
e.g. 2 cycle instructions: JMP, JZ
4 cycle instructions: MUL, DIV
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3. Instruction Timing
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4. Timers Timer mode Base 8051 has 2 timers Counter mode
we have 3 in the Atmel 89C55
Timer mode
Increments every machine cycle (12 clock cycles)
Counter mode
Increments when T0/T1 go from (external signal)
Access timer value directly
Timer can cause an interrupt
Timer 1 can be used to provide programmable baud rate for serial communications
Timer/Counter operation
Mode control register (TMOD)
Control register (TCON)
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5. Mode Control Register (TMOD)
GATE - allows external pin to enable timer (e.g. external pulse)
0: INT pin not used
1: counter enabled by INT pin (port 3.2, 3.3)
C/T - indicates timer or counter mode
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6. M1 -- Timer/counter operating mode select bit 1
M1 -- Timer/counter operating mode select bit 1. Set/cleared by program to select mode. M0 -- Timer/counter operating mode select bit 0. Set/cleared by program to select mode. Mode 0 uses 13 bit timer Mde1 uses 16 bit timer Mode2 uses 8 bit timer. Its is auto reload Mode 3 is split timer.
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7. Timer/Counter Control Register (TCON)
TR - enable timer/counter
TF - overflow flag: can cause interrupt
IE/IT - external interrupts and type control
not related to the timer/counter
TF1l
Timer 1 Overflow flag. Set when timer rolls from all 1's to 0. Cleared when processor vectors to execute interrupt service routine located at program address 001Bh.
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8. TR1l Timer 1 run control bit
TR1l Timer 1 run control bit. Set to 1 by program to enable timer to count; cleared to 0 by program to halt timer.
TF0 l Timer 0 Overflow flag. Set when timer rolls from all 1's to 0. Cleared when processor vectors to execute interrupt service routine located at program address 000Bh.
TR0 Timer 0 run control bit. Set to 1 by program to enable timer to count; cleared to 0 by program to halt timer
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9. Mode 1 same as Mode 0, but uses all 16 bits
Timer/Counter Mode 0
Mode 1 same as Mode 0, but uses all 16 bits
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10. Timer/Counter Mode 2 8-bit counter, auto-reload on overflow CSE 477
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11. Timer/Counter Mode 3 Gives an extra timer Applies to Timer/Counter 0
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12. Interrupts Allow parallel tasking
Interrupt routine runs in “background”
Allow fast, low-overhead interaction with environment
Don’t have to poll
Immediate reaction
An automatic function call
Easy to program
8051 Interrupts
Serial port - wake up when data arrives/data has left
Timer 0 overflow
Timer 1 overflow
External interrupt 0
External interrupt 1
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13. Interrupt Vector For each interrupt, which interrupt function to call
In low program addresses
Hardware generates an LCALL to address in interrupt vector
Pushes PC (but nothing else) onto the stack
RETI instruction to return from interrupt
0x00 - Reset PC address
0: 0x03 - External interrupt 0
1: 0x0B - Timer 0
2: 0x13 - External interrupt 1
3: 0x1B - Timer 1
4: 0x23 - Serial line interrupt
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14. Interrupt Enable (IE) SFR:
The interrupts of 8051 can be programmed and serviced by the microcontroller using the SFRs Interrupt Enable (IE) and Interrupt Priority (IP).
Interrupt Enable (IE) SFR:
EA:This bit is a global interrupt enable/disable bit. When set to 1, it permits individualinterrupts to be enable by their respective enable bits.
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15. ET2:Reserved for future use.
IE.6:Not implemented
ET2:Reserved for future use.
ES:Enable serial port interrupt. Set to 1 by program to enable serial port interrupt. Cleared to0 to disable serial port interrupt.
ET1:Enable (=1)/disable (=0) timer 1 interrupt
EX1:Enable (=1)/disable (=0) external interrupt 1
ET0:Enable (=1)/disable (=0) timer 0 interrupt
ET1:Enable (=1)/disable (=0) external interrupt 0
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16. Interrupt Priority (IP):
This a bit addressable register, with byte address B8H. The addresses are shown below.
The priority of the interrupts is determined by the bits of IP SFR. The bits which are set to 1,have a high priority and bits with 0 have low priority.
Interrupts with high priority can interrupt another interrupt with low priority. The lower priority interrupt is serviced after
higher priority interrupt is finished.
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17. IP.7 & IP.6: Not implemented IP.5: Reserved for future use
PS: Serial port priority interrupt
PT1: Priority of timer 1 interrupt
PX1: Priority of external interrupt 1
PT0: Priority of timer 0 interrupt P
X0: Priority of external interrupt0
CSE 477
8051 Overview