State Machines (Closed Loop / Moore) Synch 2.1  Paul R. Godin Updated: January 2008.

Slides:



Advertisements
Similar presentations
State-machine structure (Mealy)
Advertisements

Analysis of Clocked Sequential Circuits
COE 202: Digital Logic Design Sequential Circuits Part 3
CHAPTER 3 Sequential Logic/ Circuits.  Concept of Sequential Logic  Latch and Flip-flops (FFs)  Shift Registers and Application  Counters (Types,
Practice Problems 2 Latch and Flip Flop ©Paul Godin Created September 2007 Last edit Aug 2013.
Computing Machinery Chapter 5: Sequential Circuits.
Circuits require memory to store intermediate data
1 © 2014 B. Wilkinson Modification date: Dec Sequential Logic Circuits – I Flip-Flops A sequential circuit is a logic components whose outputs.
Overview Sequential Circuit Design Specification Formulation
Logic and Computer Design Fundamentals Registers and Counters
CS 151 Digital Systems Design Lecture 20 Sequential Circuits: Flip flops.
Sequential Circuits Problems(I) Prof. Sin-Min Lee Department of Mathematics and Computer Science Algorithm = Logic + Control.
COE 202: Digital Logic Design Sequential Circuits Part 4 KFUPM Courtesy of Dr. Ahmad Almulhem.
ECE 301 – Digital Electronics
C.S. Choy1 SEQUENTIAL LOGIC A circuit’s output depends on its previous state (condition) in addition to its current inputs The state of the circuit is.
ECE 301 – Digital Electronics Introduction to Sequential Logic Circuits (aka. Finite State Machines) and FSM Analysis (Lecture #17)
ECE 331 – Digital Systems Design Introduction to Sequential Logic Circuits (aka. Finite State Machines) and FSM Analysis (Lecture #19)
Asynchronous and Synchronous Counters
ETE Digital Electronics
Counter Section 6.3.
Sequential Circuit - Counter -
Sequential Circuits Chapter 4 S. Dandamudi To be used with S. Dandamudi, “Fundamentals of Computer Organization and Design,” Springer,  S.
Lecture 10 Topics: Sequential circuits Basic concepts Clocks
Registers and Counters
Asynchronous Counters with SSI Gates
ECE 331 – Digital Systems Design Sequential Logic Circuits: FSM Design (Lecture #20)
Last Mod: March 2014  Paul R. Godin Shift Registers Registers 1.1.
Rabie A. Ramadan Lecture 2
(Sequential Logic Circuit)
Synchronous Sequential Logic Part I
Synchronous Circuit Design (Class 10.1 – 10/30/2012) CSE 2441 – Introduction to Digital Logic Fall 2012 Instructor – Bill Carroll, Professor of CSE.
Digital Design Lecture 10 Sequential Design. State Reduction Equivalent Circuits –Identical input sequence –Identical output sequence Equivalent States.
Synchronous Sequential Logic Part II
Circuit, State Diagram, State Table
Rabie A. Ramadan Lecture 3
State Machines.
Sequential Circuits. Two primary differences between combinational circuits and sequential circuits –Sequential circuits are synchronous (use a clock)
Chapter 8 -- Analysis and Synthesis of Synchronous Sequential Circuits.
2017/4/24 CHAPTER 6 Counters Chapter 5 (Sections )
1 Lecture 22 Sequential Circuits Analysis. 2 Combinational vs. Sequential  Combinational Logic Circuit  Output is a function only of the present inputs.
Synch 1.1 Synchronous Counters 1 ©Paul Godin Created January 2008.
Digital
Flip Flops 3.1 Latches and Flip-Flops 3 ©Paul Godin Created September 2007 Last Edit Aug 2013.
Asynch 1.1 Asynchronous Counters 1 ©Paul Godin Last Edit Sept 2009.
1 © 2014 B. Wilkinson Modification date: Dec Sequential Logic Circuits Previously, we described the basic building blocks of sequential circuits,
Introduction to State Machine
Chapter 1 Counters. Counters Counters are sequential circuits which "count” through a specific state sequence. They can count up, count down, or count.
CHAPTER 8 - COUNTER -.
Synchronous Counters Synchronous digital counters have a common clock which results in all the flip-flops being triggered simultaneously. Consequently,
MSI Counters Counter ICs Technician Series ©Paul Godin Updated Feb 2015 gmail.com.
Analysis and Synthesis of Synchronous Sequential Circuits A “synchronizing” pulse/edge signal (clock) controls the operation of the memory portion of the.
1 State Reduction Goal: reduce the number of states while keeping the external input-output requirements unchanged. State reduction example: a: input 0.
Princess Sumaya University
Counters 2.1 MSI Counters Counter ICs ©Paul Godin Updated Aug 2013 gmail.com.
Counters.
Basic terminology associated with counters Technician Series
Learning to Design Counters
Synchronous Sequential Logic Part I
EEE515J1_L4-1/12 EEE515J1 ASICs and DIGITAL DESIGN EGBCDCNT.pdf An example of a synchronous sequential machine.
Flip Flops 4.1 Latches and Flip-Flops 4 ©Paul Godin Created September 2007 Last edit Sept 2009.
Synchronous Counter Design
Flip Flops 3.1 Latches and Flip-Flops 3 ©Paul Godin Created September 2007 Last Edit Aug 2013.
FIGURE 5.1 Block diagram of sequential circuit
Digital Design Lecture 9
T Flip-Flop A T (toggle) flip-flop is a complementing flip-flop and can be obtained from a JK flip-flop when the two inputs are tied together. When T.
Latches and Flip-Flops 2
Asynchronous Counters 2
Synchronous Counters 4: State Machine Counting
Latches and Flip-Flops 2
Basic terminology associated with counter and sequential circuits.
Presentation transcript:

State Machines (Closed Loop / Moore) Synch 2.1  Paul R. Godin Updated: January 2008

Synchronous Counters In a synchronous design, each Flip-Flop receives its own clock input, significantly reducing the instances of glitches. This module investigates how to provide a sequential output in any sequence desired. Synch 2.2

Synchronous Counters With each Flip-Flop receiving its own edge, there exists the flexibility to “steer” the output of each flip- flop independently by applying input states from an external source at the appropriate time. Synch 2.3 DQ0 or 1 Edge 0 or 1

State Machines A state machine is a device that will provide a sequence of binary numbers that may not follow a natural count sequence. An example of a state machine count: Synch State Diagram

Starting and Recycling When first applying power to the circuit the starting output is typically all low (000…). When designing a state machine this and any other unwanted state must be taken into account. Note that the recycling point is not necessarily all low (000…) Synch State Diagram

State Table Synch 2.6 PresentNext QAQA QBQB QCQC QAQA QBQB QCQC

Input versus Output states For state machine counts, the input to steer the output of each of the Flip-Flops can come from the outputs of any of the other Flip-Flops. By the use of external gates (if necessary), specific, usable sequences of Flip-Flop outputs can be used to create the necessary next input levels. K-Mapping techniques can be used to record and simplify the available outputs to create these inputs. Synch 2.7

Transition Tables It is necessary to know what inputs to the Flip-Flops are necessary to create the desired output states. Transition tables help define the operation of the Flip- Flop based on input states. Synch 2.8

Transition Tables D-Flip-Flop Transition Table The present and the next states of the outputs are indicated. The arrows indicate after the clocking edge. The input is what is required for the output transition to occur. Synch 2.9 Note: You must be able to build this table on your own.

Transition Tables J-K Flip-Flop Transition Table Indicated are the present and next Q-output states. If the flip-flop toggles or holds, indicate that binary value. Also note that both the J and K inputs need to be determined. The “X” indicates “Don’t Care” states (can be ‘1’ or ‘0’ input). Synch 2.10 Note: You must be able to build this table on your own.

J-K Flip Flop Transition Table Synch 2.11 Hold or Reset Toggle or Set Toggle or Reset Hold or Set States Note each output of the J-K Flip-Flop is the result of 2 possible states.

K-Mapping D-Flip-Flop Synch 2.12

Building a K-Map To build a K-Map the following is needed: ◦ State Diagram of the output sequence ◦ State Table of the output sequence ◦ Transition Table for the Flip-Flop we intend to use  Present and Next outputs  Necessary inputs to create those outputs Synch

K-Mapping a Sequence: Step 1 Draw the State Table and State Diagram of the output sequence. ( We will use our previous sequence example): Synch State DiagramState Table

K-Mapping a Sequence: Step 2 Determine the type of Flip-Flop and its Transition Table. For this example, we will use the D Flip-Flop: Synch 2.15 Transition Table

Present NextInput Q C Q B Q A D C D B D A K-Mapping a Sequence: Step 3 Synch 2.16 Build the State Table with the inputs indicated:

Present NextInput Q C Q B Q A D C D B D A K-Mapping a Sequence: Step 3 Synch 2.17 Build the State table with the inputs indicated: 010 Animated

K-Mapping a Sequence: Step 4 Produce K-Mapping Tables for each output: Synch QAQA QCQBQCQB Present NextInput Q C Q B Q A D C D B D A DCDC 010X010X 0XXX0XXX QAQA QCQBQCQB DBDB 110X110X 0XXX0XXX QAQA QCQBQCQB DADA 001X001X 0XXX0XXX

K-Mapping a Sequence: Step 4 Produce K-Mapping Tables for each output: Synch QAQA QCQBQCQB Present NextInput Q C Q B Q A D C D B D A DCDC 010X010X 0XXX0XXX QAQA QCQBQCQB DBDB 110X110X 0XXX0XXX QAQA QCQBQCQB DADA 001X001X 0XXX0XXX ANIMATEDANIMATED

K-Mapping a Sequence: Step 5 Simplify, using K-Mapping rules, and determine the inputs. Synch QAQA QCQBQCQB DCDC 010X010X 0XXX0XXX QAQA QCQBQCQB DBDB 110X110X 0XXX0XXX QAQA QCQBQCQB DADA 001X001X 0XXX0XXX D A =Q C D C =Q C Q B D B =Q C Q A

K-Mapping a Sequence: Step 6 Draw the Circuit Diagram, and verify its operations. Synch 2.21

K-Mapping J-K Flip-Flop Synch 2.22

Building a K-Map To build a K-Map, needed are: ◦ State Diagram of the output sequence ◦ State Table of the output sequence ◦ Transition Table for the Flip-Flop we intend to use  Present and Next outputs  Necessary inputs to create those outputs Synch

K-Mapping a Sequence: Step 1 Draw the State Table and State Diagram of the output sequence. ( We will use our previous sequence example): Synch State DiagramState Table

K-Mapping a Sequence: Step 2 Determine the type of Flip-Flop and its Transition Table. For this example, we will use the J-K Flip-Flop: Synch 2.25 Transition Table

K-Mapping a Sequence: Step 3 Synch 2.26 Build the State Table with the inputs indicated: 0 X 1 X 0 X PresentNextInput Q C Q B Q A J C K C J B K B J A K A X X 0 0 X X 1 X 1 1 X 0 X 0 X X 1

K-Mapping a Sequence Step 3 Synch X 1 X 0 X PresentNextInput Q C Q B Q A J C K C J B K B J A K A X X 0 0 X X 1 X 1 1 X 0 X 0 X X 1 Animated Build the State table with the inputs indicated:

K-Mapping a Sequence: Step 4a Produce K-Mapping Tables for each output: Synch QAQA QCQBQCQB JCJC 01XX01XX 0XXX0XXX QAQA QCQBQCQB KCKC XX1XXX1X XXXXXXXX QAQA QCQBQCQB JBJB 1XXX1XXX 0XXX0XXX 0 X 1 X 0 X PresentNextInput Q C Q B Q A J C K C J B K B J A K A X X 0 0 X X 1 X 1 1 X 0 X 0 X X 1

K-Mapping a Sequence: Step 4a Produce K-Mapping Tables for each output: Synch QAQA QCQBQCQB JCJC 01XX01XX 0XXX0XXX QAQA QCQBQCQB KCKC XX1XXX1X XXXXXXXX QAQA QCQBQCQB JBJB 1XXX1XXX 0XXX0XXX 0 X 1 X 0 X PresentNextInput Q C Q B Q A J C K C J B K B J A K A X X 0 0 X X 1 X 1 1 X 0 X 0 X X ANIMATEDANIMATED

K-Mapping a Sequence: Step 4b Produce K-Mapping Tables for each output: Synch QAQA QCQBQCQB KBKB X01XX01X XXXXXXXX QAQA QCQBQCQB JAJA 001X001X XXXXXXXX QAQA QCQBQCQB KAKA XXXXXXXX 1XXX1XXX 0 X 1 X 0 X PresentNextInput Q C Q B Q A J C K C J B K B J A K A X X 0 0 X X 1 X 1 1 X 0 X 0 X X 1

K-Mapping a Sequence: Step 5a Simplify, using K-Mapping rules, and determine the inputs. Synch 2.31 J C =Q B K C = QAQA QCQBQCQB JCJC 01XX01XX 0XXX0XXX QAQA QCQBQCQB KCKC XX1XXX1X XXXXXXXX QAQA QCQBQCQB JBJB 1XXX1XXX 0XXX0XXX J B =Q A

K-Mapping a Sequence: Step 5b Simplify, using K-Mapping rules, and determine the inputs. Synch QAQA QCQBQCQB KBKB X01XX01X XXXXXXXX QAQA QCQBQCQB JAJA 001X001X XXXXXXXX QAQA QCQBQCQB KAKA XXXXXXXX 1XXX1XXX K B =Q C J A =Q C K A =1

K-Mapping a Sequence: Step 6 Draw the Circuit Diagram, and verify its operations. Synch 2.33

Questions Which of the flop-flops is simpler to use for state machine counting? What would happen if all the flip-flops were changed from negative to positive edge devices? In what instances would we use custom count sequences? Synch 2.34

Review Customized state machine counting can be accomplished by using synchronous counter design. K-Mapping is useful in simplifying state machine design. Transition tables take the previous state into account for determining the digital state of the output. Synch 2.35

Exercise Design a counter with the following sequence: ◦ ◦ Using D-Flip Flops ◦ Using J-K Flip-Flops Verify the sequence using EWB Synch 2.36

END Synch 2.37 ©Paul R. Godin gmail.com