1. ECE 301 – Digital Electronics
Sequential Logic Circuits:
FSM Design
(Lecture #19)

2. ECE 301 - Digital Electronics
FSM Design: Procedure
Understand specifications
Derive state diagram
Create state table
Perform state minimization (if necessary)
Encode states (state assignment)
Create state-assigned table
Select type of Flip-Flop to use
Determine Flip-Flop input equations and FSM output equation(s)
Draw circuit diagram
ECE Digital Electronics

3. ECE 301 - Digital Electronics
FSM Design
Mealy Machines
ECE Digital Electronics

4. FSM Design (Mealy) Example:
Design a FSM that detects a sequence of three or more consecutive ones on an input bit stream.
The FSM should output a 1 when the sequence is detected, and a 0 otherwise.
This is another example of a sequence detector.
ECE Digital Electronics

5. FSM Design: Example (Mealy)
Input: …
Output: …
ECE Digital Electronics

6. FSM Design: Example (Mealy)
State
Diagram
State Diagram
ECE Digital Electronics

7. FSM Design: Example (Moore)
State
Diagram
ECE Digital Electronics

8. FSM Design: Example (Mealy)
State Table
Present State
Next State
Output
w = 0
w = 1 QA QB
QA+
QB+ z A B 1 C D d
Output is a function
of the present state
and the input
(Mealy Machine)
Next state is a function
of the present state
and the input
Using Binary Encoding
for the State Assignment
ECE Digital Electronics

9. FSM Design: Example (Mealy)
The choice of Flip-Flop determines the complexity of the combinational logic required in the design of the state machine.
Each type of Flip-Flop has a unique characteristic equation.
SR Flip-Flop
Q+ = S + R'.Q
D Flip-Flop
Q+ = D
JK Flip-Flop
Q+ = J.Q' + K'.Q
T Flip-Flop
Q+ = T '.Q + T.Q'
ECE Digital Electronics

10. Synthesis using D Flip-Flops (Q+ = D)
FSM Design (Mealy)
Synthesis using D Flip-Flops
(Q+ = D)
ECE Digital Electronics

11. FSM Design: Example (Mealy)
Present State
Next State
FF Inputs
w = 0
w = 1 QA QB
QA+
QB+ DA DB A 1 B C D d
ECE Digital Electronics

12. FSM Design: Example (Mealy)
ECE Digital Electronics

13. FSM Design: Example (Mealy)
ECE Digital Electronics

14. FSM Design: Example (Mealy)
Circuit Diagram
ECE Digital Electronics

15. Synthesis using JK Flip-Flops (Q+ = J.Q' + K'.Q)
FSM Design (Mealy)
Synthesis using JK Flip-Flops
(Q+ = J.Q' + K'.Q)
ECE Digital Electronics

16. FSM Design: Example (Mealy)
Excitation Table + Q Q+
ECE Digital Electronics

17. FSM Design: Example (Mealy)
Present State
Next State
FF Inputs
w = 0
w = 1 QA QB
QA+
QB+ JA KA JB KB A 1 d B C D
ECE Digital Electronics

18. FSM Design: Example (Mealy)
Karnaugh Maps
ECE Digital Electronics

19. FSM Design: Example (Mealy)
Circuit Diagram
ECE Digital Electronics

20. FSM Design (Mealy) Example:
Design a Finite State Machine (FSM) that meets the following specifications:
1. The circuit has one input, w, and one output, z.
2. All changes in the circuit occur on the positive edge of the clock.
3. The output z is equal to 1 if the pattern 010 is detected on the input w. Otherwise, the value of z is equal to 0. Overlapping sequences should not be detected.
This is another example of a sequence detector.
ECE Digital Electronics

21. FSM Design: Example (Mealy)
Input (w): …
Output (z): …
ECE Digital Electronics

22. FSM Design: Example (Mealy)
State Diagram
ECE Digital Electronics

23. FSM Design (Mealy) Example:
Design a Finite State Machine (FSM) that meets the following specifications:
1. The circuit has one input, w, and one output, z.
2. All changes in the circuit occur on the positive edge of the clock.
3. The output z is equal to 1 if the pattern 010 is detected on the input w. Otherwise, the value of z is equal to 0. Overlapping sequences should be detected.
This is another example of a sequence detector.
ECE Digital Electronics

24. FSM Design: Example (Mealy)
Input (w): …
Output (z): …
ECE Digital Electronics

25. FSM Design: Example (Mealy)
State Diagram
ECE Digital Electronics

26. FSM Design (Mealy) Example:
Design a Finite State Machine (FSM) that meets the following specifications:
1. The circuit has one input, w, and one output, z.
2. All changes in the circuit occur on the positive edge of the clock.
3. The output z is equal to 1 if the pattern 010 or the pattern 110 is detected on the input w. Otherwise, the value of z is equal to 0. Overlapping sequences should be detected.
This is example of a sequence detector that can detect 2 sequences.
ECE Digital Electronics

27. FSM Design: Example (Mealy)
Input (w): …
Output (z): …
ECE Digital Electronics

28. FSM Design: Example (Mealy)
State Diagram
ECE Digital Electronics

29. ECE 301 - Digital Electronics
Counters
ECE Digital Electronics

30. FSM Design (Counter) Example: Design a 3-bit Counter
(using the formal FSM Design Procedure)
ECE Digital Electronics

31. ECE 301 - Digital Electronics
FSM Design: Example
ECE Digital Electronics

32. ECE 301 - Digital Electronics
FSM Design: Example
What is the output of a counter?
ECE Digital Electronics

33. Synthesis using T Flip-Flops
(Q+ = T'.Q + T.Q')
ECE Digital Electronics

34. ECE 301 - Digital Electronics
FSM Design: Example +
Excitation Table
ECE Digital Electronics

35. ECE 301 - Digital Electronics
FSM Design: Example
Q+ = T.Q' + T'.Q
next state
flip-flop input
ECE Digital Electronics

36. ECE 301 - Digital Electronics
FSM Design: Example
ECE Digital Electronics

37. ECE 301 - Digital Electronics
FSM Design: Example
ECE Digital Electronics

38. Acknowledgments
The slides used in this lecture were taken, with permission, from those provided by Pearson Prentice Hall for
Digital Design (4th Edition).
They are the property of and are copyrighted by
Pearson Education.
ECE Digital Electronics