CS-280 Dr. Mark L. Hornick 1 Sequential Execution Normally, CPU sequentially executes instructions in a program Subroutine calls are synchronous to the execution of the main program Main program subroutine RCALL RET

CS-280 Dr. Mark L. Hornick 2 Consider a program that uses a subroutine to retrieve the status of a pushbutton The Get_pb subroutine can: 1. Loop continuously until the pushbutton is pressed 2. Return immediately with the current state of the pushbutton Main program Get_pb RCALL RET

CS-280 Dr. Mark L. Hornick 3 Case 1: Get_pb loops continuously until the pushbutton is pressed The main program waits until Get_pb returns Nothing can be executed in the main program in the meantime Main program Get_pb RCALL RET

CS-280 Dr. Mark L. Hornick 4 Case 2: Get_pb returns immediately with the current state of the pushbutton The main program must repeatedly call Get_pb In between whatever else it is doing What happens if the pushbutton is pressed and released between calls? Main program Get_pb RCALL RET

CS-280 Dr. Mark L. Hornick 5 Interrupts can be used to address these issues Basically, an interrupt is a hardware-generated subroutine call: When an interrupt occurs, the CPU itself (not the program) vectors to special subroutines… …called the Interrupt Service Routines Main program ISR Interrupt caused by pushbutton press RETI

CS-280 Dr. Mark L. Hornick 6 An interrupt can happen at any time while a program is running The ISR is automatically called in the middle of the running program Interrupt requests are asynchronous to the execution of the main program no “call” instruction is required (vector) Interrupts temporarily suspend “normal” program execution so the CPU can be freed to service these requests After an interrupt has been serviced, the interrupted program resumes where it was interrupted Main program ISR interrupt RETI

CS-280 Dr. Mark L. Hornick 7 On the Atmega32, there are 21 sources of hardware-generated interrupts Internal Interrupts are generated by on-chip subsytems: Power subsystem Power on, reset, voltage low… Timer/Counter subsystem Timer expired, Counter match,… More on this later in this course Analog-to-Digital Converter subsystem A/D conversion complete More on this next week Serial port (USART) Char received, Char sent,… More on this in OpSys course External Interrupts are triggered by devices interfaced to the Atmega32: Anything that can generate an “on/off” signal (+5v/0v) switches, buttons, digital output from another computer… Atmega32 has 3 pins (PD2, PD3, PB2) that the CPU “listens” to for external triggering

CS-280 Dr. Mark L. Hornick 8 When an Interrupt occurs: 1. The address of next instruction (PC) is placed on the Stack Just like an RCALL instruction does 2. Further interrupts are disabled 1. Automatically calls CLI (CLear Interrupts) 3. The CPU vectors to the ISR and begins executing it ISR is also known as an interrupt handler 4. At the end of the ISR, RETI (RETurn from Interrupt) pops the PC and normal execution resumes Compared to RET: RETI is like RET, but also restores global interrupts (auto-SEI)

CS-280 Dr. Mark L. Hornick 9 How does the CPU know which ISR to invoke? Interrupt Vectors are located in Program Memory Locations 0x0 through 0x29 Each Vector occupies 2 words (4 bytes in PM) Each Interrupt source has its own Vector You already know the Vector used for a Power-on Interrupt (0x0)

CS-280 Dr. Mark L. Hornick 10 ISR Vector locations

CS-280 Dr. Mark L. Hornick 11 SREG has a special-purpose bit (I) that enables or disables the operation of all Interrupts Normally, the I-bit is unset meaning interrupts are masked, or disabled. use SEI / CLI to set/clear the I flag

CS-280 Dr. Mark L. Hornick 12 In addition to global I-bit in SREG, most Interrupt sources are subject to local enable/disable via bits in their respective control registers For instance, External Interrupts INT0, INT1, and INT2 are individually enabled/disabled via the GICR register (at 0x3B) in I/O memory For example, to enable External Interrupt 0 (INT0), you have to set both the I-bit in SREG as well as the INT0 bit (bit 6) in GICR. Note: you can’t use the SBI instruction in GICR to set a bit SBI/CBI only works on I/O registers 0-31

CS-280 Dr. Mark L. Hornick 13 The MCU Control Register affects what triggers External Interrupts

CS-280 Dr. Mark L. Hornick 14 Interrupt I-bit in the SREG also controls the nesting of Interrupts When an ISR is invoked, the I bit is automatically cleared This prevents another interrupt from interrupting the ISR Further interrupts become pending, but not serviced The RETI instruction resets the I bit when exiting the ISR Pending interrupts then get serviced In some cases it may be useful to allow one ISR to interrupt another An ISR can explicitly set the I bit with the SEI instruction But can make things much more complicated…

CS-280 Dr. Mark L. Hornick 15 ISR Vector setup example for Reset and External Interrupts 0 and 1.NOLIST.INCLUDE "m32def.inc"; contains.EQU's for DDRB, PORTB, and a lot more.LIST.CSEG ; this means further directives are for the Code Segment.ORG 0x0 rjmp start ; initialize Reset Vector at 0x0000.ORG 0x2 rjmpint0_handler; initialize int0 Vector at 0x0002.ORG 0x4 rjmpint1_handler; intiialize int1 Vector at 0x0004

CS-280 Dr. Mark L. Hornick 16 Interrupt Latency An ISR is called after the current instruction finishes executing Latency is the lag between the time the interrupt occurs and the time it takes to start executing the ISR It is determined by the longest-running instruction (about 4 cycles – 0.25 microseconds max at 16MHz)

CS-280 Dr. Mark L. Hornick 17 If two interrupts occur at the same time, the one with the highest priority executes first All interrupts have a separate interrupt vector Interrupt priority is determined by placement of their interrupt vector position The lower the interrupt vector address, the higher the priority Example: External interrupts INT0 and INT1 occur simultaneously INT0 vector is 0x2; INT1 vector is 0x4 INT0 interrupt is serviced first

CS-280 Dr. Mark L. Hornick 18 Interrupts Summary Interrupts are enabled/disabled via the I-bit of SREG and hardware-specific control registers Interrupt Service Routines are invoked in response to an interrupt The ISR that is called depends on the source of the Interrupt ISR’s are specified via the Vectors at the beginning of Program Memory Lower vector addresses have higher priority in cases when more than one interrupt occurs simultaneously ISR’s are like subroutines, except they are called automatically through the HW interrupt mechanism The PC register is automatically pushed on the stack when an interrupt occurs The PC is popped when the ISR exits via the RETI instruction The Status Register I bit is automatically CLEARED (interrupts are disabled) when an interrupt occurs; this bit is automatically restored on RETI You can reset the I bit within an ISR if you want to enable the ISR to be interrupted The other bits in the Status Register are NOT automatically saved or restored You have to save and restore the SREG yourself