FEV And Netlists Erik Seligman CS 510, Lecture 5, January 2009

Goals  Review how logic changes in synthesis  Understand how to make RTL-netlist FEV work Mainly looking at synthesized netlists  “Grab Bag” of cool techniques for FEV Look at interesting corner cases

Synthesized Netlist Basics  Synthesized netlists built from cell library  Cells hide transistor-level logic Delivered with behavioral descriptions Library owners certify correctness  Be sure you have a library! FEVing full block at transistor level is expensive Cell and custom FEV is separate process

Custom & Cell FEV  Typically done by specialized team  FEV tools like have special functionality LEC –custom abstract logic …  Users have to give many hints to tool Transistor, pin directions Which nodes are meant to hold state Domino precharge nodes

State Negation And Replication

Are these equivalent?

Yes- State Negation is OK add mapped point f2 f4 –inv OR set mapping method -phase

Are these equivalent?

Yes- State Replication add instance equivalence f2_1 f2_2 –rev

Don’t Forget Key Point Mapping (One Representative) add instance equivalence f2_1 f2_2 –rev add renaming rule r1 f2 f2_1 -gold

Pin Replication Also Common add pin equivalence ck1 ck2 –rev add renaming rule r2 ck ck1 -gold

Scan Chains and FEV

What Is A Scan Chain?  Enable observation of internal states Critical for post-silicon debug May enable setting internal states as well May involve all (full scan) or some states  Do this by creating serial chain Minimize need for additional pins Cost: Extra wires & more complex flops

Logic Example (no scan)

Logic + Scan Chain

Handling scan chains in FEV  Be careful! Scan in netlists, but not RTL Scan insertion is during synthesis  Identify scan enable conditions May be simple scan enable pin Or combination of pins / states  Use FEV constraints to disable in netlist add pin constraint 0 scan_en –rev  Plan to address verification hole! Gate-level simulation of netlist Or custom scripts to walk chains

Clock Gating

What is Clock Gating?  Goal: Power Reduction  Stop clock to inactive flops No clock change  No switching power  Automatically inserted in synthesis Thus in netlist but not RTL

Enabled Flop (no clk gating)

Enabled Flop + Clock Gating set flatten model –gated_clock

Black Boxes

What is a Black Box?  Area of logic to ignore for FEV Usually a Verilog module instance  Why ignore some logic? Non-FEVable analog circuits “Hard IP”– externally supplied block you trust Divide & conquer– different ownership  What is verified? Drivers of bbox input pins Recipients of bbox outputs Internals are ignored– be careful!

Black Box Example add black box /top/yellow –both TOP YELLOW a b c

Black Box Example TOP.YELLOW is a single key point But mapped only if a, b, and c have matches Verify fails if logic driving a or b mismatches TOP YELLOW a b c

Don’t Care (DC) Space

Are these equal?

What if we see source RTL… case ({a,b}) 2’b00: out=0 2’b01: out=1 2’b10: out=1 endcase

What if we see source RTL… case ({a,b}) 2’b00: out=0 2’b01: out=1 2’b10: out=1 endcase Unspecified case is a Don’t-Care (DC)

Don’t Care Cases  Often result from underspecified RTL  Synthesis has freedom to choose values Can optimize for area, timing, etc.  FEV tools can handle automatically BUT DCs only come from GOLD model DC in REV model is an error (‘E’) Asymmetry between GOLD and REV!

Watch out for confusion!

Pipeline Retiming

Are these equivalent?

Yes, in a sequential sense. Logic moved across flop: Pipeline Retiming

Pipeline Retiming and FEV  Retiming violates state matching Shouldn’t expect combo FEV tool to handle  BUT recent tools can handle some cases FEV tools aware of synthesis techniques –Internally “push” logic along pipeline to match add module attribute m1 –pipeline_retime  Many limitations, be careful Retiming must be isolated to one module Can cause runtime/memory complexity Need sequential FEV for more general cases

References / Further Reading  Scan  Clock Gating 270_Fall07/PROJECT/LUO/snug2000.pdf 270_Fall07/PROJECT/LUO/snug2000.pdf =915 =915  Pipeline Retiming rces/resources_imp/verif/Dtp_cdnlive2005_1207_E mbanath.pdf rces/resources_imp/verif/Dtp_cdnlive2005_1207_E mbanath.pdf 3/2.3_paper.pdf 3/2.3_paper.pdf