1. Word-Level Aspects of ABC
Alan Mishchenko
UC Berkeley

2. Overview Data structures and exchange formats
Word-level transformations
Bit-blasting
Optimization
Word-level engines
Multiplier abstraction
Memory abstraction

3. Bit-Blasting Generate AIG for each word-level operator
Tries to minimize the number of AIG nodes
Support all major operators
Circuits can be sequential
Very fast computation (used in the inner loop)
Currently, bit-blasting is performed for each operation is isolation
A better solution is to make delay-aware or constant-propagation-aware blasting
This could result in a better circuit structure

4. Multiplier Abstraction
Many designs have multipliers
Verification without abstraction does not work
Abstraction has several “degrees of freedom”
Black-boxing
Replace each multiplier output with a new primary input
Selective black-boxing
Replace some output bits with bit-level primary inputs
Adding uninterpreted function (UIF) constraints
Without black-boxing
With black-boxing
In all these cases, the abstraction is conservative
For more info, see papers in FMCAD 2016 and 2017

5. Memory Abstraction Many designs have memories
Verification without abstraction does not work
Memories are represented using “memory primitives”
During abstraction, these are transformed in a certain way, resulting in a word-level circuit without memories
The abstraction is conservative

6. Memory Primitives READ / WRITE ports Flip-flop Multiplixer Buffer
Primary input
“Memory wire”

7. Memory Modeling Using PrimitivesRD
READ data (RD)
READ RA 
clock
MEMORY
enable
MUX
Memory wire
(yellow line) 1
enable
WRITE data (WD)
WRITE
WRITE addr (WA)
clock
READ addr (RA)
FLOP WA WD

8. Black-Boxing vs. White-Boxing
Design
Black boxing
RD1
RD2
RD3  PI PI PI
Design
No logic
RD1
RD2
RD3
Memory primitives
Design
White boxing
RD1 RA
RD2
RD3 WA WD 
Logic without mem primitives RA WA WD

9. Transformation with White-Boxing
A separate logic cone is created for each READ port
Create a new primary input to model the data output of this READ port
Replace “memory wire” by “word-level data wire” whose bit-width is equal to that of READ data
Replace memory MUXes by word-level MUXes
Replace WRITE ports by MUXes controlled by address comparators

10. Transformation of WRITE PortRD RD
READ
Data wire … 
Memory wire RA … …
MUX 1 =
WRITE WD RA WA
Data wire
Memory wire WA WD

11. Comments New primary input is added for each READ port
Separate logic cone is added for each READ port
Each primitive is modeled as discussed above
If more than one READ connects to a memory wire, READ addresses can be compared
The resulting abstraction is lossy but conservative

12. Summary Discussed word-level features of ABC
Had a closer look at memory abstraction
Models memories using “memory primitives”
Transforms them into regular word-level nodes
Can be combinational or sequential