What’s New in Xilinx Ready-to-use solutions. Key New Features of the Foundation Series 1.5/1.5i Release  New device support  Integrated design environment.

Slides:



Advertisements
Similar presentations
Xilinx 6.3 Tutorial Integrated Software Environment (ISE) Set up basic environment Select Gates or Modules to Be simulated (Insert Program Code) Run Waveform.
Advertisements

© 2003 Xilinx, Inc. All Rights Reserved Course Wrap Up DSP Design Flow.
Spartan-3 FPGA HDL Coding Techniques
EELE 367 – Logic Design Module 2 – Modern Digital Design Flow Agenda 1.History of Digital Design Approach 2.HDLs 3.Design Abstraction 4.Modern Design Steps.
© 2003 Xilinx, Inc. All Rights Reserved Architecture Wizard and PACE FPGA Design Flow Workshop Xilinx: new module Xilinx: new module.
Graduate Computer Architecture I Lecture 15: Intro to Reconfigurable Devices.
How to use the VHDL and schematic design entry tools.
VHDL Synthesis in FPGA By Zhonghai Shi February 24, 1998 School of EECS, Ohio University.
Implementation of DSP Algorithm on SoC. Mid-Semester Presentation Student : Einat Tevel Supervisor : Isaschar Walter Accompaning engineer : Emilia Burlak.
Foundation and XACTstepTM Software
© 2011 Xilinx, Inc. All Rights Reserved This material exempt per Department of Commerce license exception TSU Xilinx Tool Flow.
StateCAD FPGA Design Workshop. For Academic Use Only Presentation Name 2 Objectives After completing this module, you will be able to:  Describe how.
ISE. Tatjana Petrovic 249/982/22 ISE software tools ISE is Xilinx software design tools that concentrate on delivering you the most productivity available.
© 2003 Xilinx, Inc. All Rights Reserved CORE Generator System.
Automating Database Processing Chapter 6. Chapter Introduction Design and implement user-friendly menu – Called navigation form Macros – Automate repetitive.
ASIC/FPGA design flow. FPGA Design Flow Detailed (RTL) Design Detailed (RTL) Design Ideas (Specifications) Design Ideas (Specifications) Device Programming.
Foundation Express The HDL Value Leader. Xilinx Foundation Express The HDL Value Leader  Complete HDL Development Environment Best in Class EDA Tools.
Simulink ® Interface Course 13 Active-HDL Interfaces.
Xilinx Development Software Design Flow on Foundation M1.5
© 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only Xilinx Design Flow FPGA Design Flow Workshop.
Xilinx Programmable Logic Design Solutions Version 2.1i Designing the Industry’s First 2 Million Gate FPGA Drop-In 64 Bit / 66 MHz PCI Design.
COE 405 Design and Modeling of Digital Systems
IEEE ICECS 2010 SysPy: Using Python for processor-centric SoC design Evangelos Logaras Elias S. Manolakos {evlog, Department of Informatics.
Interfaces to External EDA Tools Debussy Denali SWIFT™ Course 12.
09/04/971 Xilinx Cadence Alliance Series Technology through Teamwork.
Developing software and hardware in parallel Vladimir Rubanov ISP RAS.
OVERVIEW OF OVERVIEW OF Spartan-3. DESIGNFLOW Translate Map Place & Route Plan & Budget HDL RTL Simulation Synthesize to create netlist Functional Simulation.
Programmable Logic Training Course Project Manager.
This material exempt per Department of Commerce license exception TSU Xilinx Tool Flow.
Fall 08, Oct 31ELEC Lecture 8 (Updated) 1 Lecture 8: Design, Simulation Synthesis and Test Tools ELEC 2200: Digital Logic Circuits Nitin Yogi
Lecture #2 Page 1 ECE 4110– Sequential Logic Design Lecture #2 Agenda 1.Logic Design Tools Announcements 1.n/a.
Programmable Logic Training Course HDL Editor
CPE 626 Advanced VLSI Design Lecture 6: VHDL Synthesis Aleksandar Milenkovic
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU FPGA Design with Xilinx ISE Presenter: Shu-yen Lin Advisor: Prof. An-Yeu Wu 2005/6/6.
Introductory project. Development systems Design Entry –Foundation ISE –Third party tools Mentor Graphics: FPGA Advantage Celoxica: DK Design Suite Design.
HARDWARE DESCRIPTION LANGUAGE (HDL). What is HDL? A type of programming language for sampling and modeling of electronic & logic circuit designs It can.
Tools - Design Manager - Chapter 6 slide 1 Version 1.5 FPGA Tools Training Class Design Manager.
Tools - LogiBLOX - Chapter 5 slide 1 FPGA Tools Course The LogiBLOX GUI and the Core Generator LogiBLOX L BX.
CORE Generator System V3.1i
© 2003 Xilinx, Inc. All Rights Reserved Course Wrap Up DSP Design Flow.
ELEE 4303 Digital II Introduction to Verilog. ELEE 4303 Digital II Learning Objectives Get familiar with background of HDLs Basic concepts of Verilog.
Teaching Digital Logic courses with Altera Technology
FOUNDATION Series Software Foundation v1.5 Enhancements Version 2.0.
Xilinx Academy 4/98 1 Xilinx Software Solutions Xilinx Academy November, 1998.
Ready to Use Programmable Logic Design Solutions.
FOUNDATION Series Software Foundation Series v1.5i Xilinx Academy Foundation Series Software Technical Marketing Spring 1999 notes pages are used with.
WebPOWERED Software Solutions – Spring 2000 WebPOWERED CPLD Software Solutions SPRING OF CY2000.
ASIC/FPGA design flow. Design Flow Detailed Design Detailed Design Ideas Design Ideas Device Programming Device Programming Timing Simulation Timing Simulation.
VHDL From Ch. 5 Hardware Description Languages. History 1980’s Schematics 1990’s Hardware Description Languages –Increased due to the use of Programming.
© 2005 Xilinx, Inc. All Rights Reserved This material exempt per Department of Commerce license exception TSU CORE Generator System.
1 2/1/99 Confidential Selling Xilinx Software vs. Altera Xilinx Academy February 24th, 1999.
Design with Vivado IP Integrator
Altera Technical Solutions Seminar Schedule OpeningIntroduction FLEX ® 10KE Devices APEX ™ 20K & Quartus ™ Overview Design Integration EDA Integration.
1 Introduction to Engineering Spring 2007 Lecture 18: Digital Tools 2.
Xilinx Alliance Series Xilinx/Synopsys Powerful High Density Solutions
Xilinx Alliance Series
M1.5 Foundation Tools Xilinx XC9500/XL CPLD
Introduction to Programmable Logic
Xilinx Ready to Use Design Solutions
Programmable Logic Design Solutions
FPGA Tools Course Answers
ECE 699: Lecture 3 ZYNQ Design Flow.
Powerful High Density Solutions
VHDL Introduction.
THE ECE 554 XILINX DESIGN PROCESS
Digital Designs – What does it take
THE ECE 554 XILINX DESIGN PROCESS
Xilinx CPLD Software Solutions
Xilinx Alliance Series
Presentation transcript:

What’s New in Xilinx Ready-to-use solutions

Key New Features of the Foundation Series 1.5/1.5i Release  New device support  Integrated design environment with advanced design flow automation control  Full verilog support  “Point” tool productivity enhancements Design tools Synthesis Implementation tools  Web-enabled Design Features

Foundation Series 1.5 New Device Support  XC9500 XL - true ISP, 3.3V cplds  Spartan XL - no compromise architecture at 3.3V  Virtex - system level programmable logic  Continued device support for: Xc3000x, xc3100x, XC4KX, XC5200, XC9500, spartan

Foundation Series 1.5 Integrated Design Environment  Synopsys FPGA Express 2.1 directly embedded within foundation PCM  Xilinx implementation tools with A.K.A. Speed Technology embedded within PCM  Aldec’s Active-VHDL direct push button interface (purchased as an option from Aldec)

Foundation Series 1.5 Full Verilog Support  State Editor Now Generates Verilog HDL  Full HDL Editor Support Color Coding Language Assistant Verilog Templates Verilog HDL Syntax Checking  Schematic Editor Supports Verilog Modules (Macros)  Verilog Source Code Debugging via MTI* * Evaluation copies of ModelSim are included with all Foundation Series HDL packages. Licensed, Sold, and Supported separately by Model Technology Inc.

 Synthesis (FPGA Express)  Implementation Tools (A.K.A. Speed Technology)  Schematic Editor  HDL Editor  Gate Level Simulator Foundation Series 1.5 Point Tool Enhancements

Point Tool Enhancements Express Synthesis  Embedded with foundation series PCM  Virtex specific optimization  Addition of important VHDL ‘93 constructs End keyword-component keyword Is keyword-labels on assignments T’image(x)-block in generate Alias keyword-array slices with others  Addition of other HDL constructs Rising_edge / falling_edge ‘Else Hex, octal and binary for std_logic_vectors

 State machine synthesis options FSM Encoding Style One Hot Binary FSM Extraction Method Safest (all possible states) Smallest (defined states only) Point Tool Enhancements Express Synthesis

 Embedded within foundation series PCM  A.K.A. Speed technology Device floorplanner Xilinx constraints editor New timespecs Temperature pro-rating Min-delays K-paths timing analysis algorithm Point Tool Enhancements Implementation Tools

Point Tool Enhancements Schematic Editor  Re-implemented bus behavior Complex buses Bus editing now similar to wire editing  Enhanced wire behavior Selection, deletion Autowiring / rubberbanding  Local menus (e.g., right-click > hierarchy push, copy/paste, symbol properties, etc.)  “SC symbols” dialog box enhanced - project components separated from unified library comps

Point Tool Enhancements Schematic Editor (continued)  “Replace symbol” option now has a drop-down selector from which to pick new symbol  Symbol attributes can now be moved directly (no need to bring up properties dialog)  Multi-level undo (5 levels)  Copy/paste enhancement: objects to be pasted are visible as copy buffer is moved around on the schematic  Enhanced CORE generator 1.5 interface (i.E., Symbol generation)

Point Tool Enhancements HDL Editor  New “insert file” item in edit menu Provides easy method for insertion of logiblox and CORE generator created instantiation templates  Verilog syntax checking, color-coding, language templates, schematic flow macro synthesis  VHDL language assistant templates updated to be express compliant

Point Tool Enhancements Gate-Level Simulator  Virtex LUT support Some limitations at first release; may be addressed in performance pack Typical user will want to use behavioral simulator anyway  Memory allocation tuning to support larger netlists  Signal selection dialog “search” feature enhanced

Point Tool Enhancements Gate-Level Simulator (continued)  New simulation script wizard Invoke at script editor start-up or Invoke from script editor’s tools menu  “Enable global netlist analysis” feature May speed up simulation if disabled Project-specific (not always needed)

Foundation Series 1.5 Web-enabled Design Features  Integrated into Project Manager  Instant Access to  Netscape and MS Explorer compatible News Bulletins Searchable Knowledge Base (includes agent reports) Designer Tools & Services