DPI+ Proposals John Stickley, Duaine Pryor Mentor Emulation Division
Copyright © , Mentor Graphics. Mentor Graphics Confidential DPI+ Proposals 2 Existing Requirements n Long standing requirements for SCE-MI I — Performance in emulated environments — Transaction oriented — Support for multi-threaded C/C++/HVL TB modeling environments — Multi-lingual on HDL side (Verilog, VHDL) n Previously discussed requirements for SCE-MI II (fall 2003): — No more uncontrolled time — Variable length messages
Copyright © , Mentor Graphics. Mentor Graphics Confidential DPI+ Proposals 3 New Requirements ? n Fusion, alignment with other standards efforts n Emphasis on ease of use for the user and the model writer n Model reusability n Determinism (a.k.a. repeatability) n Streaming support (while retaining determinism) n Synchronization to (not just “support for”) multi- threaded C++ environments n Easy mapping to accelerator platforms (synthesizeability)
Copyright © , Mentor Graphics. Mentor Graphics Confidential DPI+ Proposals 4 Existing Standards – Abstraction Space “Sweet Spots” TLM Untimed SystemC Only DPI Untimed ANSI C, C++, SystemC SCE-MI Untimed ANSI C, C++, SystemC PLI/VPI Timed C Messages (big vectors)SignalsParametrized TLM FIFOsFunction Calls + Arguments HVL/C/C++ Abstraction Conduits HDL Abstraction Behavioral HDL, “RTL+” CC* HDL (can be synthesizeable) RTL CC* HDL (synthesizeable) What is TLM here ? Is it behavioral ? (Is it synthesizeable ?) Behavioral HDL, RTL CC* HDL (partly synthesizeable), Timed gate level *TLM WG term for “cycle callable” meaning “cycle accurate”
Copyright © , Mentor Graphics. Mentor Graphics Confidential DPI+ Proposals 5 Proposal for DPI+ n Is there some “common ground” for existing transaction based modeling standards ? n Can parts be combined where they are serving the same conceptual purpose ? n Can the combined standard still meet past and current requirements ? n Can the combined standard leverage existing, implemented, proven standards without re-inventing the wheel ?
Copyright © , Mentor Graphics. Mentor Graphics Confidential DPI+ Proposals 6 Proposed Standards – Abstraction Space “Sweet Spots” TLM Untimed SystemC Only DPI+ Untimed ANSI C, C++, SystemC PLI/VPI Timed C SignalsParametrized TLM FIFOsFunction Calls + Arguments HVL/C/C++ Abstraction Conduits HDL Abstraction Behavioral HDL, “RTL+” CC* HDL (can be synthesizeable) Behavioral HDL, RTL CC* HDL (partly synthesizeable), Timed gate level What is TLM here ? Is it behavioral ? (Is it synthesizeable ?) *TLM WG term for “cycle callable” meaning “cycle accurate”
Copyright © , Mentor Graphics. Mentor Graphics Confidential DPI+ Proposals 7