George Mason University ECE 448 – FPGA and ASIC Design with VHDL FPGA Devices ECE 448 Lecture 5

2 Required reading Spartan-6 FPGA Configurable Logic Block: User Guide  CLB Overview  Slice Description

3 Highly recommended for the Wednesday lab section using Nexys 4 boards 7 Series FPGAs Configurable Logic Block: User Guide  Overview  Functional Details Recommended reading

4ECE 448 – FPGA and ASIC Design with VHDL Block RAMs Configurable Logic Blocks I/O Blocks What is an FPGA? Block RAMs

5 Modern FPGA Graphics based on The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. ( Multipliers/DSP units RAM blocks Logic resources (#Logic resources, #Multipliers/DSP units, #RAM_blocks)

6ECE 448 – FPGA and ASIC Design with VHDL Major FPGA Vendors SRAM-based FPGAs Xilinx, Inc. Altera Corp. ( subsidiary of Intel since 2015) Lattice Semiconductor Atmel Achronix Tabula (went out of business in 2015) Flash & antifuse FPGAs Microsemi SoC Products Group (formerly Actel Corp.) Quick Logic Corp. ~ 51% of the market ~ 34% of the market ~ 85%

7ECE 448 – FPGA and ASIC Design with VHDL Xilinx  Primary products: FPGAs and the associated CAD software  Main headquarters in San Jose, CA  Fabless* Semiconductor and Software Company  UMC (Taiwan) {*Xilinx acquired an equity stake in UMC in 1996}  Seiko Epson (Japan)  TSMC (Taiwan)  Samsung (Korea) Programmable Logic Devices ISE Alliance and Foundation Series Design Software

TechnologyLow-costMid-rangeHigh- performance 220 nmVirtex 180 nmSpartan-II, Spartan-IIE 120/150 nmVirtex-II, Virtex-II Pro 90 nmSpartan-3Virtex-4 65 nmVirtex-5 45 nmSpartan-6 40 nmVirtex-6 28 nmArtix-7Kintex-7Virtex-7 Xilinx FPGA Families

9 FPGA Family

10ECE 448 – FPGA and ASIC Design with VHDL Spartan-6 FPGA Family

11ECE 448 – FPGA and ASIC Design with VHDL Artix-7 FPGA Family

George Mason University ECE 448 – FPGA and ASIC Design with VHDL CLB Structure

13ECE 448 – FPGA and ASIC Design with VHDL The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. ( General structure of an FPGA

14ECE 448 – FPGA and ASIC Design with VHDL Xilinx Spartan-6 & Artix-7 CLB

15ECE 448 – FPGA and ASIC Design with VHDL Row & Column Relationship Between CLBs & Slices

16ECE 448 – FPGA and ASIC Design with VHDL Basic Components of the Slice LUTs Storage Elements

17ECE 448 – FPGA and ASIC Design with VHDL Example of a 4-input LUT (Look-Up Table) (used in earlier families of FPGAs) Look-Up tables are primary elements for logic implementation Each LUT can implement any function of 4 inputs

18ECE 448 – FPGA and ASIC Design with VHDL LUT of Spartan-6 and Artix-7

19

20ECE 448 – FPGA and ASIC Design with VHDL Reset and Set Configurations No set or reset Synchronous set Synchronous reset Asynchronous set (preset) Asynchronous reset (clear)

21ECE 448 – FPGA and ASIC Design with VHDL Three Different Types of Slices in Spartan-6 50%25%

22ECE 448 – FPGA and ASIC Design with VHDL Two Different Types of Slices in Artix-7

23ECE 448 – FPGA and ASIC Design with VHDL SLICEX

24 SLICEL

25  Each SliceL and SliceM contains separate logic and routing for the fast generation of sum & carry signals Increases efficiency and performance of adders, subtractors, accumulators, comparators, and counters  Carry logic is independent of normal logic and routing resources Fast Carry Logic LSB MSB Carry Logic Routing

26 Accessing Carry Logic  All major synthesis tools can infer carry logic for arithmetic functions Addition (SUM <= A + B) Subtraction (DIFF <= A - B) Comparators (if A < B then…) Counters (count <= count +1)

27ECE 448 – FPGA and ASIC Design with VHDL

28ECE 448 – FPGA and ASIC Design with VHDL SLICEM

29 The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. ( Xilinx Multipurpose LUT (MLUT) 64 x 1 ROM (logic) 64 x 1 RAM 32-bit SR

30 Single-port 64 x 1-bit RAM

31 Single-port 64 x 1-bit RAM

32 Memories Built of Neighboring MLUTs Single-port 128 x 1-bit RAM: RAM128x1S Dual-port 64 x 1-bit RAM : RAM64x1D Memories built of 2 MLUTs: Memories built of 4 MLUTs: Single-port 256 x 1-bit RAM: RAM256x1S Dual-port 128 x 1-bit RAM: RAM128x1D Quad-port 64 x 1-bit RAM:RAM64x1Q Simple-dual-port 64 x 3-bit RAM:RAM64x3SDP (one address for read, one address for write)

33 Dual-port 64 x 1 RAM Dual-port 64 x 1-bit RAM : 64x1D Single-port 128 x 1-bit RAM: 128x1S

34 Dual-port 64 x 1 RAM ECE 448 – FPGA and ASIC Design with VHDL Dual-port 64 x 1-bit RAM : 64x1D Single-port 128 x 1-bit RAM: 128x1S

35 Total Size of Distributed RAM in Spartan-6

36 Total Size of Distributed RAM in Artix-7

37ECE 448 – FPGA and ASIC Design with VHDL MLUT as a 32-bit Shift Register (SRL32)

George Mason University ECE 448 – FPGA and ASIC Design with VHDL Input/Output Blocks (IOBs)

39ECE 448 – FPGA and ASIC Design with VHDL Basic I/O Block Structure D EC Q SR D EC Q SR D EC Q SR Three-State Control Output Path Input Path Three-State Output Clock Set/Reset Direct Input Registered Input FF Enable

40ECE 448 – FPGA and ASIC Design with VHDL IOB Functionality IOB provides interface between the package pins and CLBs Each IOB can work as uni- or bi-directional I/O Outputs can be forced into High Impedance Inputs and outputs can be registered advised for high-performance I/O Inputs can be delayed

George Mason University ECE 448 – FPGA and ASIC Design with VHDL Family Attributes

42ECE 448 – FPGA and ASIC Design with VHDL Spartan-6 FPGA Family

43ECE 448 – FPGA and ASIC Design with VHDL Artix-7 FPGA Family

44ECE 448 – FPGA and ASIC Design with VHDL FPGA device present on the Digilent Nexys 3 board XC6SLX16-CSG324C Spartan-6 family Size 324 pins Package type (Ball Chip-Scale) Commercial temperature range 0° C – 85° C Logic Optimized

45ECE 448 – FPGA and ASIC Design with VHDL FPGA device present on the Digilent Nexys 4 DDR board XC7A100T-1CSG324C Artix-7 family Size 324 pins Package type (Ball Chip-Scale) Commercial temperature range 0°C – 85° C Speed Grade