Raw Status Update Chips & Fabrics James Psota M.I.T. Computer Architecture Workshop 9/19/03

Psota | CAW ‘032 Talk Outline 1. Raw Hardware Update –Recent progress –Specs –Plans 2. Raw Fabric System –Design Goals –Architecture Overview –Design Challenges

Psota | CAW ‘033 Raw Chips!

Psota | CAW ‘034 Raw “Handheld” Board First program, 80MHz (January 2003) “Thorough testing,” 300MHz (May 2003) Currently 2 handheld boards, 10 more on the way

Psota | CAW ‘035 Raw Chip Specifications IBM SA27E Process –0.15 , 6-metal copper ASIC process 16 Tile RAW Processor –18.23mm x 18.23mm –1657 pin CCGA package –1152 signal pins Clock and Power –420MHz (actual) –10 watts (power save mode) –18 watts typical –35 watts max

Psota | CAW ‘036 Performance Overview Raw Chip (at 420MHz) – 7 GOPS/GFLOPS (single precision) – 100 GB/s of on-chip memory bandwidth – 90 GB/s of on-chip “bisection bandwidth” – 40 GB/s I/O bandwidth No bugs so far!

Psota | CAW ‘037 Current Work and Plans -Continuing evaluation and experimentation -Building embedded applications: -Embedded networking board -Audio beamformer system -Chroma keying system b,g,a wireless system -Virtual x86 emulation layer -Incorporating higher bandwidth IO interfaces (PCI, USB2) -Will help us realize RAW’s potential

Psota | CAW ‘038 Raw Fabric System 1024 tile processors –64 Raw chips –0.5 teraflops total bit PCI slots USB2 and 4GB SDRAM “Year 2010 Prototype” System (Oxygen)

Psota | CAW ‘039 Fabric System Architecture Design: two distinct board types Board 1: Quad Raw Board Board 2: I/O & Memory Board Replicate and connect HOW???

Psota | CAW ‘0310 The Challenge How do we use the same board designs for every position in the fabric? CPU board is easy enough.

Psota | CAW ‘0311 The Challenge How do we use the same board designs for every position in the fabric? E.g., I/O board

Psota | CAW ‘0312 The Saman Flip How do we use the same IO board design for every position in the fabric? Make symmetric about x-axis Compensate for board flip in firmware BEFORE X AFTER

Psota | CAW ‘0313 Quad Board 4 RAW chips per board pin MICTOR connectors total (4 per side) Power distributed over separate cables from other signals MICTOR connectors are stacked to save space

Psota | CAW ‘0314 Quad Board Layout 11”

Psota | CAW ‘0315 I/O & Memory Board 4 FPGAs 2 64-bit PCI slots 2 Expansion Ports 4 SDRAM banks 11”

Psota | CAW ‘0316 Clock Distribution signal generated and distributed from a center board over MICTOR connectors uses DLLs to deskew the clock at each connection every quad board sends and receives a copy of the clock to its neighbors and we can select which of the input clocks to use using dip switches clock generator

Psota | CAW ‘0317 Clock Distribution from external input DLL Synchronized clocks for all Raw chips in fabric Delay-Locked Loop uses feedback to tune delay line for clock synchronization Dip switches keep clock dist. general  no custom firmware

Psota | CAW ‘0318 Power Distribution distributed separately from signals external power supply feeds top and bottom rows of I/O Boards power supply

Psota | CAW ‘0319 Power Distribution 48V distributed to all boards, then down-converted locally DC-DC converters on each board –1.8V Raw core –1.5V Raw I/O –3V other logic –1.5V is also further down converted to 0.75V supply for HSTL termination System-wide power supply can be up to 3kW At 1.8V, 64 Raw chips can draw 1280 amps!!!

Psota | CAW ‘0320 Reset Distribution signal generated by one of the I/O boards and distributed over MICTOR connectors reset originates here

Psota | CAW ‘0321 Fabric Schedule Quad Board routing has begun IO Board layout completed by late September Both boards fabbed and assembled by November

Raw Status Update Chips & Fabrics James Psota M.I.T. Computer Architecture Workshop 9/19/03