1 COMP541 Finite State Machines - 1 Montek Singh Sep 22, 2014

Today’s Topics  State Machines How to design machines that go through a sequence of events How to design machines that go through a sequence of events  “sequential machines” Basically: Close the feedback loop in this picture: Basically: Close the feedback loop in this picture: 2

What is sequential logic?  Anything that is not combinational has a cycle of gates has a cycle of gates output cannot be determined solely by the current inputs output cannot be determined solely by the current inputs i.e., has state i.e., has state  But: Not all sequential circuits are useful e.g., 3-inverter loop e.g., 3-inverter loop  is sequential because of feedback  but not controllable by a clock  Synchronous sequential logic: a useful form follows a specific template follows a specific template 3

Synchronous Sequential Logic  Flip-flops/registers contain the system’s state state changes only at clock edge state changes only at clock edge  so system is synchronized to the clock all flip-flops receive the same clock signal (important!) all flip-flops receive the same clock signal (important!) every cyclic path must contain a flip-flop every cyclic path must contain a flip-flop

Synchronous Sequential Logic  Flip-flops/registers contain the system’s state state changes only at clock edge state changes only at clock edge  so system is synchronized to the clock all flip-flops receive the same clock signal (important!) all flip-flops receive the same clock signal (important!) every cyclic path must contain a flip-flop every cyclic path must contain a flip-flop

Examples  Some of these are synchronous sequential circuits, but some are not! Which ones? 6

Two common types  Two common types of synchronous sequential circuits: Finite State Machines (FSMs) Finite State Machines (FSMs) Pipelines Pipelines 7

Finite State Machine (FSM)  Consists of: State register that State register that  holds the current state  updates it to the “next state” at clock edge Combinational logic (CL) that Combinational logic (CL) that  computes the next state –using current state and inputs  computes the outputs –using current state (and maybe inputs)

More and Mealy FSMs  Two types of finite state machines differ in the output logic: Moore FSM: Moore FSM:  outputs depend only on the current state Mealy FSM: Mealy FSM:  outputs depend on the current state and the inputs can convert from one form to the other can convert from one form to the other  Mealy is more general, more expressive  In Both: Next state is determined by current state and inputs Next state is determined by current state and inputs

Moore and Mealy FSMs 10

FSM Example 1 11

Traffic Light Controller  Traffic light controller Traffic sensors: T A, T B (TRUE when there’s traffic) Traffic sensors: T A, T B (TRUE when there’s traffic) Lights: L A, L B Lights: L A, L B

FSM Black Box  Inputs: CLK, Reset, T A, T B CLK, Reset, T A, T B  Outputs: L A, L B

FSM Specification  When reset, L A is green and L B is red  As long as traffic on Academic (T A high), keep L A green  When T A goes low, sequence to traffic on Bravado  Follow same algorithm for Bravado  Let’s say clock period is 5 sec (time for yellow light) 14

States  What sequence do the traffic lights follow? Reset  State 0, L A is green and L B is red Reset  State 0, L A is green and L B is red Next (on board)? Next (on board)? 15

State Transition Diagram  Moore FSM: outputs labeled in each state outputs labeled in each state states: circles states: circles transitions: arcs transitions: arcs

State Transition Table  state graph encoded into a tabular format

“Encoded” State Transition Table  Symbolic states assigned bit codes codes can be arbitrarily chosen codes can be arbitrarily chosen  some are better than others (  “optimal state coding”)

After Input and Output Encoding  Inputs and outputs assigned bit codes again, codes can be arbitrarily chosen again, codes can be arbitrarily chosen  again, some are better than others

FSM Schematic: State Register

Next State Logic

Output Logic

FSM Timing Diagram: Study carefully!

24 Design Procedure  Step-by-step procedure: given FSM description: codify it into a state diagram or table given FSM description: codify it into a state diagram or table assign codes to the states, inputs and outputs assign codes to the states, inputs and outputs derive Boolean equations and implement derive Boolean equations and implement  Or, write Verilog and compile the compiler follows the above steps the compiler follows the above steps uses algorithms for optimal coding of states/inputs/outputs uses algorithms for optimal coding of states/inputs/outputs uses algorithms for optimal Boolean implementation uses algorithms for optimal Boolean implementation

FSM Example 2 25

26 A Sequence Recognizer  Circuit has input, X, and output, Z  Recognizes sequence 1101 on X Specifically: Specifically:  if X has been 110 and next bit is 1, make Z high

27 How to Design States  States remember past history Clearly must remember we have seen 110 when next 1 comes along Clearly must remember we have seen 110 when next 1 comes along Tell me one necessary state for this example…? Tell me one necessary state for this example…?

28 Beginning State  Start state: let’s call it A if 1 appears on input, move to next state B if 1 appears on input, move to next state B output remains at 0 output remains at 0 Input / Output

29 Second 1  New state, C  To reach C, must have seen 11

30 Next a 0  If 110 has been received, go to D  Next 1 will generate a 1 on output Z

31 What else?  What happens to arrow on right? Must go to some state. Where? Must go to some state. Where?

32 What Sequence?  Here we have to interpret the problem statement  We have just seen 01 Is this beginning of new 1101? Is this beginning of new 1101? Or do we need to start over w/ another 1? Or do we need to start over w/ another 1?  Let us say that it is the beginning of a new run…

33 Cover every possibility  Must cover every possibility out of every state For every state: X = 0 or 1 For every state: X = 0 or 1 You fill in all the cases You fill in all the cases

34 Fill in

35 Full Answer

36 State Minimization  Do we need all those states? Some may be redundant Some may be redundant  How to use as few states as possible?  State minimization is a well-studied problem Is a tough problem (NP-complete) Is a tough problem (NP-complete)  but pretty good algorithms exist  exact and approximate Out of the scope of this course Out of the scope of this course

FSM implementation  Do yourself: State transition table State transition table State encoding State encoding Truth tables Truth tables Boolean equations and gate-level implementation Boolean equations and gate-level implementation 37

Lab 6 Preview Buttons and Debouncing 38

Lab Preview: Buttons and Debouncing  Mechanical switches “bounce” vibrations cause them to go to 1 and 0 a number of times vibrations cause them to go to 1 and 0 a number of times  called “chatter” hundreds of times! hundreds of times!  We want to do 2 things: “Debounce”: Any ideas? “Debounce”: Any ideas? Synchronize with clock Synchronize with clock  i.e., only need to look at it at the next +ve edge of clock  Think about (for Wed class): What does it mean to “press the button”? Think carefully!! What does it mean to “press the button”? Think carefully!! What if button is held down for a long time? What if button is held down for a long time? 39

40Reading  Read entire 3.3 and 3.4