1. 1 CS 140 Lecture 9 Sequential Networks Professor CK Cheng CSE Dept. UC San Diego

2. 2 Combinational CLK A BC D Sequential Networks 1.Components F-Fs 2.Specification 3.Implementation: Excitation Table

3. 3 Specification Finite State Machine: –Input Output Relation –State Diagram –State Table Circuit: –Logic Diagram –Netlist –Boolean Expression

4. 4 Netlist  State Table  State Diagram  Input Output Relation y(t) = Q 1 (t)Q 0 (t) Q 0 (t+1) = D 0 (t) = x(t)Q 1 (t) Q 1 (t+1) = D 1 (t) = x(t) + Q 0 (t) x Q0Q0 Q1Q1 D Q Q’ D Q y Q1Q1 Q0Q0 D1D1 D0D0 Clk

5. 5 Netlist  State Table  State Diagram  Input Output Relation x Q0Q0 Q1Q1 D Q Q’ D Q y Q1Q1 Q0Q0 D1D1 D0D0 y(t) = Q 1 (t)Q 0 (t) Q 0 (t+1) = D 0 (t) = x(t)Q 1 (t) Q 1 (t+1) = D 1 (t) = x(t) + Q 0 (t) Clk

6. 6 State table 0 00 11 01 10 00 11 01 1 PS input x=0 x=1 00, 0 10, 0 10, 0 00, 0 11, 0 10, 1 11, 1 Q 1 (t) Q 0 (t) Q 1 (t+1) Q 0 (t+1), y(t) S0S1S2S3S0S1S2S3 PS input x=0 x=1 S 0, 0 S 2, 0 S 2, 0 S 0, 0 S 3, 0 S 2, 1 S 3, 1 Let: S 0 = 00 S 1 = 01 S 2 = 10 S 3 = 11 Remake the state table using symbols instead of binary code, e.g. ’00’ y(t) = Q 1 (t) Q 0 (t) Q 0 (t+1) = D 0 (t) = x(t) Q 1 (t) Q 1 (t+1) = D 1 (t) = x(t) + Q 0 (t) Logic Diagram => State Table

7. 7 State Table => State Diagram Example: Output sequence S0S1S2S3S0S1S2S3 PS input x=0 x=1 S 0, 0 S 2, 0 S 2, 0 S 0, 0 S 3, 0 S 2, 1 S 3, 1 x/y S1S1 S2S2 S3S3 S0S0 0,1/0 1/0 0/1 1/0 0/0 1/1 Time012345 Input01101- StateS0 S2S3S2S3 Output000101

8. 8 y(t) = Q 1 (t)Q 0 (t) Q 0 (t+1) = T 0 (t) = x(t) Q 1 (t) Q 1 (t+1) = T 1 (t) = x(t) + Q 0 (t) X T Q Q’ T Q y Q0Q0 Q1Q1 T0T0 T1T1 Example with T Flip-Flops

9. 9 Logic Diagram => Excitation Table => State Table y(t) = Q 1 (t)Q 0 (t) T 0 (t) = x(t) Q 1 (t) T 1 (t) = x(t) + Q 0 (t) Q 0 (t+1) = T 0 (t) Q’ 0 (t)+T’ 0 (t)Q 0 (t) Q 1 (t+1) = T 1 (t) Q’ 1 (t)+T’ 1 (t)Q 1 (t) idQ 1 (t)Q 0 (t)xT 1 (t)T 0 (t)Q 1 (t+1)Q 0 (t+1)y 000000000 100110100 201010110 301110110 410000100 510111010 611010011 711111001 Excitation Table

10. 10 idQ 1 (t ) Q 0 (t)xT 1 (t)T 0 (t)Q 1 (t+1)Q 0 (t+1)y 000000000 100110100 201010110 301110110 410000100 510111010 611010011 711111001 Excitation Table =>State Table => State Diagram 0/0 S0 S1S3 S2 0/0 1/1 0/1 0, 1/01/0 PS\InputX=0X=1 S0S0,0S2,0 S1S3,0 S2S2,0S1,0 S3S1,1S0,1 State Assignment S0 00 S1 01 S2 10 S3 11

11. 11 Excitation Table =>State Table => State Diagram 0/0 S0 S1S3 S2 0/0 1/1 0/1 0, 1/01/0 PS\InputX=0X=1 S0S0,0S2,0 S1S3,0 S2S2,0S1,0 S3S1,0S0,1 Time012345 Input01101- StateS0 S2S1S3S0 Output000010 Example: Output sequence

12. 12 Implementation: State Diagram => State Table => Netlist Pattern Recognizer: A sequential machine has a binary input x in {a,b}. For x(t-2, t) = aab, the output y(t) = 1, otherwise y(t) = 0. S1 S0 a/0 b/0 a/0 b/1 S2 a/0 b/0

13. 13 State Diagram => State Table with State Assignment State Assignment S0: 00 S1: 01 S2: 10 PS\xab S0S1,0S0,0 S1S2,0S0,0 S2S2,0S0,1 PS\x01 0001,000,0 0110,000,0 1010,000,1 Q 1 (t+1)Q 0 (t+1), y a 0 b 1

14. 14 State Table => Excitation Table PS\x01 0001,000,0 0110,000,0 1010,000,1 idQ1Q0xQ1Q0xD1D0D1D0 y 0000010 1001000 2010100 3011000 4100100 5101001 6110--- 7111---

15. 15 0 2 6 4 1 3 7 5 x(t) Q1Q1 0 1 - 1 0 0 - 0 Q0Q0 D 1 (t): D 1 (t) = x’Q 0 + x’Q 1 D 0 (t)= Q’ 1 Q’ 0 x’ y= Q 1 x idQ1Q0xQ1Q0xD1D0D1D0 y 0000010 1001000 2010100 3011000 4100100 5101001 6110--- 7111--- Excitation Table => Boolean Expression

16. 16 D Q Q’ D Q Q1Q1 Q0Q0 D1D1 D0D0 Q0Q0 Q1Q1 x’ D 1 (t) = x’Q 0 + x’Q 1 D 0 (t)= Q’ 1 Q’ 0 x’ y= Q 1 x x y Q’ 1 Q’ 0 x’

17. 17 Canonical Form: Mealy and Moore Machines Combinational Logic x(t) y(t) CLK C2 C1 y(t) CLK x(t) C1C2 CLK x(t) y(t)

18. 18 Moore Machine: y i (t) = f i (X(t), S(t)) Mealy Machine: y i (t) = f i (S(t)) s i (t+1) = g i (X(t), S(t)) C1C2 CLK x(t) y(t) Mealy Machine C1C2 CLK x(t) y(t) Moore Machine s(t) Canonical Form: Mealy and Moore Machines

19. 19 Finite State Machine Example Traffic light controller –Traffic sensors: T A, T B (TRUE when there’s traffic) –Lights: L A, L B

20. 20 FSM Black Box Inputs: CLK, Reset, T A, T B Outputs: L A, L B

21. 21 FSM State Transition Diagram Moore FSM: outputs labeled in each state States: Circles Transitions: Arcs

22. 22 FSM State Transition Diagram Moore FSM: outputs labeled in each state States: Circles Transitions: Arcs

23. 23 FSM State Transition Table PSInputsNS TATA TBTB S00XS1 S01X S1XXS2 X0S3 S2X1 S3XXS0

24. 24 State Transition Table PSInputsNS Q 1 (t)Q 0 (t)TATA TBTB Q 1 (t +1)Q 0 (t +1) 000X01 001X00 01XX10 10X011 10X110 11XX00 StateEncoding S000 S101 S210 S311 Q 1 (t+1)= Q 1 (t)  Q 0 (t) Q 0 (t+1)= Q’ 1 (t)Q’ 0 (t)T’ A + Q 1 (t)Q’ 0 (t)T’ B

25. 25 FSM Output Table PSOutputs Q1Q1 Q0Q0 LA1LA1 LA0LA0 LB1LB1 LB0LB0 000010 010110 101000 111001 OutputEncoding green00 yellow01 red10 L A1 = Q 1 L A0 = Q’ 1 Q 0 L B1 = Q’ 1 L B0 = Q 1 Q 0

26. 26 FSM Schematic: State Register

27. 27 Logic Diagram

28. 28 FSM Schematic: Output Logic