Meenakshi Kaul, Vinoo Srinivasan, Sriram Govindarajan, Iyad Ouaiss, and Ranga Vemuri University of Cincinnati Partitioning and Synthesis for Run-Time Reconfigurable Computers Using the SPARCS System

SPARCS System Pre-Processor Temporal Partitioning Spatial Partitioning High-Level Synthesis Logic/Layout Synthesis Estimates Based on Light-Weight High-Level Synthesis Estimates Based on Light-Weight High-Level Synthesis Estimates Based on Light-Weight Layout Synthesis Estimates Based on Light-Weight Layout Synthesis Bitmap files HOST Reconfiguration Schedule Reconfiguration Schedule Multi-FPGA board Multi-FPGA board Behavior Spec. Constraints RTL design+ Floorplan Target Architecture Target Architecture Macro-Library SPARCS Core

FPGA CONFIGURATION MEMORY(ROM) SHARED MEMORY ( RAM ) SHARED MEMORY ( RAM ) FPGA INTERCONNECTION NETWORK LOCAL MEMORY LOCAL MEMORY LOCAL MEMORY LOCAL MEMORY LOCAL MEMORY LOCAL MEMORY LOCAL MEMORY LOCAL MEMORY INPUTS OUTPUTS SPARCS Goal SpecificationArchitecture Binding T1 T3 T4 I/O M1 M2 M4 T2 M3 memory segment dependency channel design task I/O environment task channel

Configure Execute Temporal Partitioning: Goal TEMPORAL PARTITIONS Reconfiguration Schedule TASK GRAPH T4 T1 T2 T3 T1 T4 T3 T2 DESIGN POINTS FOR TASKS Map tasks to temporal partitions. Map tasks to design points. Latency minimization. T4 T1 T2 T3

Temporal Partitioning: Approach Architecture ConstraintsBeh. Specification High-Level Synthesis Estimator Tool High-Level Synthesis Estimator Tool Preprocessing Unit Preprocessing Unit Partition Bounds Estimator Partition Bounds Estimator N = Min. P Temporal Partitions YES Relax Number of Partitions (N= N+1) Linear Programming Model Solve for Constraint Satisfaction Solve for Constraint Satisfaction Latency Bounds Estimator for N partitions Latency Bounds Estimator for N partitions Solution Found? Reduce Latency Bounds YES Stop Is N < Max.P No

Spatial Partitioner Partition Cost Evaluator LW High Level Synthesis Task dependency Graph, Parameterized Component Library Target Architecture Model, Spatial Partitioning: Goal Partitioning of the tasks with FPGA mapping T1, T2T3T4,T5 FPGA1 FPGA2FPGA3 Partitioning of logical Memories with mapping M2M4, M3M1, T5 LM 1 LM 2LM 3 Interconnect Synthesis A unified Specification model that captures Set of tasks, memories and interconnections T = { T1, T2 … T5} M = {M1, M2 … M5} I = { I1, I2 … I10}

Cost Function SS Cost = S max AA A max + PP P max + II I max + MM M max + Where A max, S max, P max, I max, and M max represent the area constraint, speed constraint, pin constraint, interconnect constraint, and memory constraint.  A,  S,  P,  I, and  M are the respective constraint violation values for a given chromosome c Genetic Partitioning Evaluate current population constraint satisfying solution found Increment Generation Max generations reached No Stop Create Initial Population of partitions Yes Evolve next generation (selection, crossover and mutation) Spatial Partitioning: Approach

High Level Synthesis

UC’s DSS (Distributed Synthesis System) tailored for SPARCS. Accepts clock period and FPGA resource constraints. Layout integration for accurate estimates. Light-weight mode. Scheduling – Resolves memory conflicts. – Handles user time constraints. – Design estimation. (rough & quick or accurate & slow) Controller model – Collection of communicating synchronous FSMs. – Facilitates memory access resolution. – Root FSM generates finish_signal for a task. – Done_signal = AND ( ALL finish_signal) High Level Synthesis

Case Study: JPEG Partial Task Graph of 4x4 DCT JPEG flow

Temporal & Spatial Partitions of 4x4 DCT Case Study: Results

Static-JPEGDynamic-JPEG Case Study: Results