Fundamentals of Programming Languages-II Subject Code: 110010 Teaching Scheme Examination Scheme Theory: 1 Hr./Week Online Examination: 50 Marks Practical: 2 Hrs./Week

Unit-I Microprocessors and Micro-Controllers Architectures and Programming Concepts

Microprocessors

1.1 Features of 386DX Microprocessors It has 32-bit address bus and a 32-bit data bus. It is a 32-bit processor. The 32-bit ALU allows to process 32-bit data. It has 32-bit address bus. So it can access up to 4 Gbyte (232) physical memory or 64 terabyte(246) of virtual memory. It runs with speed up to 20 Mhz instructions per second. The pipelined architecture of the 80386DX, allows simultaneous instruction fetching, decoding, execution and memory management.

It allows programmers to switch between different operating systems such as PC-DOS and UNIX. It can operate on 17 different data types. It has built-in virtual memory management circuitry and protection circuitry required to operate an 80386DX in these modes. The 80386DX can operate in real mode, protected mode or a variation of protected mode called virtual 8086 mode.

In real mode it functions basically as a fast 8086 or real mode 80286 The 80386DX microprocessor is compatible with their earlier 8086, 8088, 80186, 80188, 80286 chips. Virtually anything that runs under these microprocessors will also run under the 80386.

1.2 Functional Block Diagram of 80386DX The internal architecture of 80386DX is divided into 3 sections Central processing unit Execution unit Instruction decode unit Memory management unit Segmentation unit Paging unit Bus Control unit

These units operate in parallel These units operate in parallel. Fetching, decoding, execution, memory management and bus accesses for several instructions are performed simultaneously. This parallel operation is called pipelined instruction processing. Execution Unit The execution unit reads the instruction from the instruction queue and executes the instructions. It consists of three subunits: Control unit, data unit and protection test unit.

Architecture of 80386 Three Sections: Bus Interface units Central Processing Unit Memory Management Unit

Control unit: It contains microcode and special hardware Control unit: It contains microcode and special hardware. The microcode and special hardware allows 80386DX to reduce time required for execution of multiply and divide instructions. It also speeds the effective address calculation. Data Unit: The data unit contains the ALU, eight 32-bit general purpose registers and a 64-bit barrel shifter. The barrel shifter is used for multiple bit shifts in one clock. Thus it increases the speed of all shift and rotate operations. The multiple/divide logic implements the bit-shift-rotate algorithms to complete the operations in minimum time.

Instruction Decode Unit Protection test unit: The protection test unit checks for segmentation violations under the control of the microcode. Instruction Decode Unit The instruction decode unit takes instruction bytes from the code pre fetch queue and translates them into microcode. The decoded instructions are then stored in the instruction queue. They are passed to the control section for deriving the necessary control signals.

Segmentation Unit Paging Unit The segmentation unit translates logical addresses into linear addresses at the request of the execution unit. The segmentation unit compares the effective address for the length limit specified in the segment descriptor. The segment unit adds the segment base and the effective address to generate linear address. Paging Unit It organizes the physical memory in terms of pages of 4 Kbytes size each.

Instruction Pre fetch Unit Bus Control Unit It communicates with the outside world. It provides a full 32-bit bi-directional data bus and 32-bit address bus. It controls the interface to external bus masters and coprocessors. Instruction Pre fetch Unit The instruction pre fetch unit fetches sequentially the instruction byte stream from the memory.

MCQs The 80386 is a _____ bit microprocessor. 16 20 32 64 The ALU of 80386 is _____ bit

The address bus of 80386DX is ___bit. 16 32 20 64 The 80386DX can address up to ___ physical memory. 1 Mbytes 16 Mbytes 1 Gbytes 4 Gbytes

1.3 CONCEPT OF MACHINE CYCLE

The steps performed by the computer processor for each machine language instruction received. The machine cycle is a 4 process cycle that includes reading and interpreting the machine language, executing the code and then storing that code.

Four steps of Machine cycle Fetch - Retrieve an instruction from the memory. Decode - Translate the retrieved instruction into a series of computer commands. Execute - Execute the computer commands. Store - Send and write the results back in memory.

Thank You