XLV INTERNATIONAL WINTER MEETING ON NUCLEAR PHYSICS Tiago Pérez II Physikalisches Institut For the PANDA collaboration FPGA Compute node for the PANDA DAQ and Trigger Motivation Panda DAQ Description of the Compute Nodes Crate System: ATCA

Tiago Pérez: FPGA Compute Nodes for Panda Bormio, 16 th January 2007 XLV International winter meeting2/10 Interaction rate of 10 Mio events/s Expected data rate: GB/s Impossible (complicated) to store to disk –Need to pre-processing and online selection –BUT: Commercial computing solutions do not fulfil our needs neither in bandwidth nor in computing power Motivation Dedicated processors with very large I/O bandwidth based on FPGAs FPGA: Field Programmable Gate Array A device where you can have whatever logic you need

Tiago Pérez: FPGA Compute Nodes for Panda Bormio, 16 th January 2007 XLV International winter meeting3/10 DAQ features Triggerless Data Acquisition (DAQ) System Continuously sampling DAQ : flash ADCs –“self-triggered” detector front end –Local feature extraction Parametrized pulse shapes Local cluster finding High quality clock distributed detector wide –Jitter ~ 25ps –Each signal gets a timestamp –Necessary for event bulding

Tiago Pérez: FPGA Compute Nodes for Panda Bormio, 16 th January 2007 XLV International winter meeting4/10 DAQ architecture Detector data concentrator Switch L1 farm L2 farm L3 farm Switch L1outL2outL3out DetIn DETECTOR FRONT END ELECTRONICS DATA OUT K. Korcyl, J. Otwinowski, Krakow Univ.

Tiago Pérez: FPGA Compute Nodes for Panda Bormio, 16 th January 2007 XLV International winter meeting5/10 Why a Compute Node Data Concentrator L1 farm –L1 trigger –Feature extraction TPC online tracking Need of a compute device with large compute power, local memory and I/O capabilities FPGA Compute Node

Tiago Pérez: FPGA Compute Nodes for Panda Bormio, 16 th January 2007 XLV International winter meeting6/10 Compute Nodes Features Prototype under development (Giessen/Beijing) Universal highly configurable and scalable hardware platform for multiple applications Resources –4 FPGAs + local dram –High speed I/O capabilities –4 x Gbit Ethernet –4 x Optical links –2 Embedded PPC on each FPGA Can run a normal Linux –Large number of logic cells –ATCA crate architecture

Tiago Pérez: FPGA Compute Nodes for Panda Bormio, 16 th January 2007 XLV International winter meeting7/10 Compute Nodes Optic fiber ports Optic fiber ports Gbit Ethernet FPGA

Tiago Pérez: FPGA Compute Nodes for Panda Bormio, 16 th January 2007 XLV International winter meeting8/10 Alternatives to FPGA nodes Comparison to a general PC: Faster: –User can change the hardware configuration (custom processing blocks) –Parallelization BUT: –More complicated to program (VHDL instead of C++) Comparison to an ASIC (Application Specific Integrated Circuit) –ASIC can be faster than a FPGA-based computer BUT: –once build can not be changed –very long and expensive developing

Tiago Pérez: FPGA Compute Nodes for Panda Bormio, 16 th January 2007 ATCA: Advance Telecommunication Crate Architecture New Telecom. Standard (rev1 2003, rev2 2005) –Becoming a particle physics standard 19” Rack: 14 slot – 8U Cooling: Classic air flow (fans) Power ~ 200W/slot Full mesh backplane with serial differential lines –Bandwidth 2TB/s

Tiago Pérez: FPGA Compute Nodes for Panda Bormio, 16 th January 2007 XLV International winter meeting10/10 summary & outlook Large data rates, Gbit/s –Normal CPU solution not viable –Need of custom made computing device DAQ architecture overview FPGA based compute node on development –Components and form factor defined –Next: Draw the Layout –Configuration and programming in testing (ML403 Xilinx dev board, M. Liu - Giessen)

Tiago Pérez: FPGA Compute Nodes for Panda Bormio, 16 th January 2007 Mechanics Advanced Mezzanine Card – Double-Width (4U), – Full-Height (1 card per 1/2slot)