1. Status Report of CN Board Design Zhen’An LIU Representing Trigger Group, IHEP, Beijing Panda DAQ Meeting, Munich Dec. 4 2007

2. Zhen'An LIU2 Outline  Review  Components  Design status

3. Dec.4 2007Zhen'An LIU3 Features Universal high performance platform for multiple applications  High Performance Compute Power: 5x (Virtex-4 FPGA + 2Gb DDR2)  ~32Gbps Bandwidth 13x RocketIO to backplane 5x Gigabit Ethernet 8x Optical Link  2 Embedded PowerPC in each FPGA Real time Linux  ATCA compliant

4. Dec.4 2007Zhen'An LIU4 Block Diagram

5. Dec.4 2007Zhen'An LIU5 FPGA Diagram

6. Dec.4 2007Zhen'An LIU6 Key Components  FPGA: Xilinx Virtex-4 FX60 (in hand)  CPLD: Xilinx XC95144XL (ordered)  Power modules: TYCO, TI (ordered)  PHY: MARVELL 88E1111 (in hand)  DDR2 SDRAM: Micron MT47H128M16 (?)  Optical transceiver: Avago HFBR5921 (in hand)  Flash Memory: Intel PC28F256P33B85 (ordered)

7. Dec.4 2007Zhen'An LIU7 Others bought or ordere except 5

8. Dec.4 2007Zhen'An LIU8 Components missing  SODIMM FOXCONN AS0A42x-N4Sx-xx. The price is about RMB24/pc, and the MOQ is 560.  RJ45 we ordered the 60 pcs  SAMTEC 60PIN CONNCTOR. we asked tiago for help in Giessen, (we need 4 pcs for each board)  MAX16003ETE, Maxim. The vendor said that it will be 17 weeks to get the components. failed to ask for samples. digikey (de.digikey.com). We need 1 pcs for each board.  7511B11, CML. 3 high light pipe used on front panel. The digikey part number on digikey web is L70580-ND. We need 8 pcs for each board.

9. Dec.4 2007Zhen'An LIU9 old Plan (Sep. 20 2007)  Schematic has been finished 15 Apr. V1.0 20 Aug. V1.1  Components are under booking  Layout is under way  PCB version 1.0 will be finished before November.

10. Dec.4 2007Zhen'An LIU10 Current Status(1)  Layer Stacks More space needed for routing, so number of layers Changed from 12 to14 layers in total 8 Signal layers 3 GND layers 3 VCC layes

11. Dec.4 2007Zhen'An LIU11 Current Status(2) Layout of DDR2 SODIMM  Hardware and layout design must be considered carefully for DDR2 SDRAM memory interfaces: Serpentine loops to match the data lane within 10 mils, All data lanes are matched with 0.5 inch, …

12. Dec.4 2007Zhen'An LIU12 Current Status(3)  Time Consuming: DDR2 socket Interconnection  85% finished DDR2 SODIMM Virtex4-FX60 Optical Transceivers Gigabit Ethernet Power Modules

13. Dec.4 2007Zhen'An LIU13  Thanks