DEEP-3 Decryption and Encryption of MP3. Structure of Presentation Project Brief Aims and Goals Partitioning Design Route ASIP Design Route Application.

Slides:



Advertisements
Similar presentations
FPGA (Field Programmable Gate Array)
Advertisements

Hao wang and Jyh-Charn (Steve) Liu
TIE Extensions for Cryptographic Acceleration Charles-Henri Gros Alan Keefer Ankur Singla.
1 SECURE-PARTIAL RECONFIGURATION OF FPGAs MSc.Fisnik KRAJA Computer Engineering Department, Faculty Of Information Technology, Polytechnic University of.
Software Engineering CSE470: Process 15 Software Engineering Phases Definition: What? Development: How? Maintenance: Managing change Umbrella Activities:
1/1/ / faculty of Electrical Engineering eindhoven university of technology Introduction Part 3: Input/output and co-processors dr.ir. A.C. Verschueren.
Alternate Software Development Methodologies
Lecture 9: Coarse Grained FPGA Architecture October 6, 2004 ECE 697F Reconfigurable Computing Lecture 9 Coarse Grained FPGA Architecture.
Zheming CSCE715.  A wireless sensor network (WSN) ◦ Spatially distributed sensors to monitor physical or environmental conditions, and to cooperatively.
Extensible Processors. 2 ASIP Gain performance by:  Specialized hardware for the whole application (ASIC). −  Almost no flexibility. −High cost.  Use.
Chapter 16 Control Unit Operation No HW problems on this chapter. It is important to understand this material on the architecture of computer control units,
Microprocessors Introduction to ia64 Architecture Jan 31st, 2002 General Principles.
Chapter 16 Control Unit Implemntation. A Basic Computer Model.
Chapter 4 Processor Technology and Architecture. Chapter goals Describe CPU instruction and execution cycles Explain how primitive CPU instructions are.
State Machines Timing Computer Bus Computer Performance Instruction Set Architectures RISC / CISC Machines.
©TheMcGraw-Hill Companies, Inc. Permission required for reproduction or display. COMPSCI 125 Introduction to Computer Science I.
Dynamically Reconfigurable Architectures: An Overview Juanjo Noguera Dept. Computer Architecture (DAC-UPC)
Chapter 2: Impact of Machine Architectures What is the Relationship Between Programs, Programming Languages, and Computers.
Chapter 15 IA 64 Architecture Review Predication Predication Registers Speculation Control Data Software Pipelining Prolog, Kernel, & Epilog phases Automatic.
Software System Integration
Study of AES Encryption/Decription Optimizations Nathan Windels.
1  Staunstrup and Wolf Ed. “Hardware Software codesign: principles and practice”, Kluwer Publication, 1997  Gajski, Vahid, Narayan and Gong, “Specification,
L29:Lower Power Embedded Architecture Design 성균관대학교 조 준 동 교수,
Dillon: CSE470: SE, Process1 Software Engineering Phases l Definition: What? l Development: How? l Maintenance: Managing change l Umbrella Activities:
Basics and Architectures
RUP Implementation and Testing
Operating Systems for Reconfigurable Systems John Huisman ID:
Automated Design of Custom Architecture Tulika Mitra
Research on Reconfigurable Computing Using Impulse C Carmen Li Shen Mentor: Dr. Russell Duren February 1, 2008.
LOGO Hardware side of Cryptography Anestis Bechtsoudis Patra 2010.
Testing Workflow In the Unified Process and Agile/Scrum processes.
Digital Design and Computer Architecture Dr. Robert D. Kent LT Ext Lecture 1 Introduction.
Mahesh Sukumar Subramanian Srinivasan. Introduction Embedded system products keep arriving in the market. There is a continuous growing demand for more.
SPREE RTL Generator RTL Simulator RTL CAD Flow 3. Area 4. Frequency 5. Power Correctness1. 2. Cycle count SPREE Benchmarks Verilog Results 3. Architecture.
J. Christiansen, CERN - EP/MIC
Configurable, reconfigurable, and run-time reconfigurable computing.
1 Towards Optimal Custom Instruction Processors Wayne Luk Kubilay Atasu, Rob Dimond and Oskar Mencer Department of Computing Imperial College London HOT.
Chapter 8 CPU and Memory: Design, Implementation, and Enhancement The Architecture of Computer Hardware and Systems Software: An Information Technology.
“Politehnica” University of Timisoara Course No. 2: Static and Dynamic Configurable Systems (paper by Sanchez, Sipper, Haenni, Beuchat, Stauffer, Uribe)
Ted Pedersen – CS 3011 – Chapter 10 1 A brief history of computer architectures CISC – complex instruction set computing –Intel x86, VAX –Evolved from.
Computer Engineering 1502 Advanced Digital Design Professor Donald Chiarulli Computer Science Dept Sennott Square
Development of Programmable Architecture for Base-Band Processing S. Leung, A. Postula, Univ. of Queensland, Australia A. Hemani, Royal Institute of Tech.,
By Edward A. Lee, J.Reineke, I.Liu, H.D.Patel, S.Kim
CPS 4150 Computer Organization Fall 2006 Ching-Song Don Wei.
Software Development Life Cycle (SDLC)
Survey of multicore architectures Marko Bertogna Scuola Superiore S.Anna, ReTiS Lab, Pisa, Italy.
CS 351/ IT 351 Modeling and Simulation Technologies HPC Architectures Dr. Jim Holten.
Basic Elements of Processor ALU Registers Internal data pahs External data paths Control Unit.
Lx: A Technology Platform for Customizable VLIW Embedded Processing.
3/12/2013Computer Engg, IIT(BHU)1 INTRODUCTION-1.
FDR--ECE6276 Class Project 12/06/00 The ChooChoo: Final Design Review Wody-Instruction Set Architecture School of Electrical and Computer Engineering Georgia.
CISC. What is it?  CISC - Complex Instruction Set Computer  CISC is a design philosophy that:  1) uses microcode instruction sets  2) uses larger.
New-School Machine Structures Parallel Requests Assigned to computer e.g., Search “Katz” Parallel Threads Assigned to core e.g., Lookup, Ads Parallel Instructions.
CPIT Program Execution. Today, general-purpose computers use a set of instructions called a program to process data. A computer executes the.
Addressing modes, memory architecture, interrupt and exception handling, and external I/O. An ISA includes a specification of the set of opcodes (machine.
Introduction Edited by Enas Naffar using the following textbooks: - A concise introduction to Software Engineering - Software Engineering for students-
Architecture & Organization 1
Overview Introduction General Register Organization Stack Organization
Hardware Support for Embedded Operating System Security
Introduction Edited by Enas Naffar using the following textbooks: - A concise introduction to Software Engineering - Software Engineering for students-
Architecture & Organization 1
Central Processing Unit
Dynamically Reconfigurable Architectures: An Overview
CISC AND RISC SYSTEM Based on instruction set, we broadly classify Computer/microprocessor/microcontroller into CISC and RISC. CISC SYSTEM: COMPLEX INSTRUCTION.
Software System Integration
Control Unit Introduction Types Comparison Control Memory
The performance requirements for DSP applications continue to grow and the traditional solutions do not adequately address this new challenge Paradigm.
Overview of Computer Architecture and Organization
Lecture 4: Instruction Set Design/Pipelining
Presentation transcript:

DEEP-3 Decryption and Encryption of MP3

Structure of Presentation Project Brief Aims and Goals Partitioning Design Route ASIP Design Route Application Choice Project Management Early Feedback What Next Conclusions

Project Brief Problem –How easy is it to harness the power of re- configurable computing? –How easy is it for Software Engineers?

Introduction What is re-configurable computing? –“Computing platforms whose architecture can be modified by software to suit the application in question. Such a system may take the form of a Field Programmable Gate Array (FPGA) combined with external memories and processors.” Why is it of such great interest? –Reduced development costs –Reduced time to market –Hot upgrades –Improved performance (sometimes!)

Current Trends in Reconfigurable Computing Greater number of gates / higher clock frequencies  increased performance Greater volumes  reduced costs C-like hardware description languages  development accessible to software engineers  more effort can be allocated to other parts of the project

Project Aims To investigate hardware/software co-design methods –By considering two design routes using a non-trivial application as a test-bench –By measuring amount of effort required for each design route –Using direct and indirect measures e.g. Lines of code, number of gates used and execution time Perceived complexity –Comparing the performance of the prototypes with the software only version

Project Goals To produce and demonstrate two working prototypes To benchmark the prototypes and the software only solution

Hardware / Software Partitioning

Partitioning Methodology (1) C Source developed using Rapid Application Development, then evolved to fixed point implementation –Common to both routes Profiling –Find “Hot spot” regions within the C source

Partitioning Methodology (2) Partitioning –Done manually as automated solutions are not very good –Apply partitioning rules C  Handel C Design inter/intra process communication, control and synchronisation Co-Simulation –For Verification and Validation

Partitioning Design Route Advantages –Conceptually simpler to understand –De Facto Standard therefore more applied examples –Method can be used to produce low power, low cost or high performance Disadvantages –Done manually –Repeated for every application

ASIP Design

ASIP Methodology (1) C Source same as Partitioning method Profiling same as Partitioning method –Also perform static analysis to discover instruction mix and number of registers required Instruction Set Architecture developed using coarse grain customisation GCC used as re-targetable compiler Simulate to validate making necessary changes

ASIP Methodology (2) RISC (Load Store) Architecture –Based on MIPS –Efficient pipelining –Higher degree of parallelism –Performance advantage Harvard Architecture –Difficult so use Von Neuman in early stages VLIW –Improves performance –Only If Time Allows

ASIP Design Route Advantages –Most of the development effort is writing C –More efficient use of function units than GP –Shorter time to market than more customised hardware design –Reusability Disadvantages –Extra complexity with compiler alterations

System Overview Local Storage Distributor MP3 Encoding MP3 Decoding Encrypted MP3 Decrypted MP3 Sound Sample Decrypted Decompressed Sound Sample Output Source Input Source Perceived as a non-trivial application -Both computationally intensive on their own -Different instruction mix (MP3 uses reals crypto uses integers)

Requirements Functional Requirements –Compress & Encrypt Sound –Decrypt, Decompress & Playback Non-Functional Requirements –Security –Multiple Input formats –Real Time –User Friendly

MP3 International Standard –ISO/IEC :1993 Legal Issues –Patented technology –Can be licensed Based on Psycho-Acoustics model –How the human mind perceives sound

MP3 Encoding Data sent as audio frames Difficult to generate a good perceptual model –Very few good quality implementations

MP3 Decoding Easier than encoding Intended playback through speakers via FPGA

MP3 Codec Selection Considered many alternatives –LAME, BlandEnc, Xing, FhG Criteria used –VBR, Fixed Point, Open Source, Sound Quality, Frequency of Public Domain Usage, Independent Tests LAME “best” –No Fixed Point

Cryptography Requirements –Open Standard, Industry Strength, Integrity Check, Authentication Legal Issues –Patents, Key Strengths Algorithms –Public / Private Key, One-Way Hashes, Digital Signatures

RSA Algorithm Security lies in intangibility of factoring large integers Key distribution problem –Compare Padlock & Key Algorithm based on fast modular exponentiation. –Good test of FPGA performance

RSA Walkthrough Diagram Here

Conceptual Model & Walkthrough Login –Related to encryption

Encoding & Encryption

Decryption & Playback

System Architecture DMA Host CPU (x86) RC-1000 Board (FPGA – Memory) Storage Device Memory (RAM) Sound Card SpeakersLine In CD-ROM Microphone PCI Bus IDE Bus

FPGA Board Architecture

Time Management Application developed rapidly Leave adequate time for –Testing –Integration –Implementation (Handel C) –Derived from reviewing why previous group’s system failed to be delivered on schedule

Risk Management – Identified Risks ASIP Design –No prior experience –Conceptually More challenging Resources –Limited availability of FPGA Handel C –No prior experience before project Task Complexity Time Management –Slow Start

Risk Management – Managing Risks Spiral Model –Incremental with regular reviews Buddy Buddy System Dedicated Handel C “expert” Achievable goals Plenty of Research

Early Feedback Profiling results –Early identification of “hotspot” functions as psycho analysis and Huffman coding Metrics –One week to grasp partitioning –Ten weeks to grasp ASIP design Handel C –Simple programs implemented

What Next? First Application Prototype –Software only Second Prototype –Fixed Point, software only Incrementally More Complex Handel C coding Further prototypes with the design processes

Summary Presented the project aims and vision Presented two opposing development methods Presented an overview of the application to be used Identified risks and how to manage them Presented initial results Planned further work

Conclusion Project remains on schedule Good progress made Lots more to do