EEE2243 Digital System Design Chapter 6: Datapath Component by Muhazam Mustapha, February 2011

Learning Outcome By the end of this chapter, students are expected to understand the design, operation and block diagram of the following datapath components: Register and register file Shifter, counter, incrementer Comparator Adder, subtractor, multiplier and ALU

Chapter Content Register and Register File Shifter Counter, Incrementer and Timer Comparator Adder, Subtractor, Multiplier Arithmetic and Logic Unit Modular Verilog

Datapath Component

Datapath Component Datapath component is a collection of memory and computation circuits that when put together and with proper control, can perform a larger scale of operation In previous chapters we have covered many of the components like: Counter, Decoder and Multiplexer We will go into more details on the components that we already covered, and some new ones Vahid 4.1 pg 167

Register & Register File

Register A collection of flip-flops used to store data or maintain states in FSM In normal operations registers load on every clock pulse In datapath operation we need to set the register to load only when we want it to D Q I 2 3 Q2 Q3 Q1 Q0 1 clk 4-bit register load

Conditional Parallel Load In datapath operation register load operations are mostly parallel – only communication applications use serial mode load The load operation however, needs to be done when a LOAD signal is on This can be done in BEHAVIORAL approach using a 2-to-1 mux at D input diagram on next slide The LOAD signal will determine either the flip-flop is to be loaded with new data or maintain current data by feedback

Conditional Parallel Load Vahid Figure 4.1 pg 169

Parallel Register Example Q3 Q2 Q1 Q0 a3 a2 a1 a0 I 3 2 1 ld R1 R0 R2 clk

Shift Register In some applications, datapath operations need to perform serial computation This can be done using shift register Shift register operates by transferring flip-flop’s bit content to neighboring flip-flop in the same register while maintaining the conditional LOAD operation Both SHIFT and LOAD operation are conditional Some shift registers may have parallel LOAD operation as well Vahid pg 173

Datapath Implementation Shift Register shr_in Implementation: Connect flip-flop output to next flip-flop’s input Datapath Implementation Vahid Figure 4.10 pg 174

Rotate Register Bit coming out from one end will go into the other end Exercise: Draw out yourself the datapath implementation of rotate register Vahid Figure 4.11 pg 174

More Complicated Register Behavioral control of register by mux can already provide us a good number of features The following is a register with 2 control line: s1 s0 Operation Functions: Maintain present value 1 Parallel load 1 Shift right 1 1 Load zero Vahid Figure 4.13 pg 176

Boolean Algebra Approach Register Design For some performance improvement, Boolean algebra design can be used, but we won’t go into too much detail: Q2 Q1 Q0 Q3 I 2 1 3 s1 shr_in shr shl ld s0 shl_in c ombi- n a tional ci r cuit s1 = ld’*shr’*shl + ld’*shr*shl’ + ld’*shr*shl s0 = ld’*shr’*shl + ld Vahid pg 177-178

Register File In some designs we may require too many registers In such designs we might be using too many wires and may cause congestions or we may exceed the synthesizable limit for no. lines This can be solve by sharing lines – BUS The registers will be accessed through address and only connect to the bus lines when selected There will be many High-Z capable connections Vahid 4.10 pg 225

Register File Vahid Figure 4.78 (modified), 4.79, 4.80 32 2 W_data W_addr W_en R_data R_addr R_en 4x32 register file Vahid Figure 4.78 (modified), 4.79, 4.80

Register File Timing Diagram 32 2 W_data W_addr W_en R_data R_addr R_en 4x32 register file Vahid Figure 4.82

Shifter

Shifter Shift register makes transfer between memory elements (flip-flop) to achieve shifting effect We can speed up the shift process if we remove the memory element since we don’t have to wait for the clock pulse to actually make the shift happens This fast shifting is required especially if the shifting is done to get the effect of multiplication by powers of 2 Shifter is the datapath component that does this with only multiplexers – no D flip-flop Vahid 4.8 pg 210

Shifter i2 q3 q2 q1 q0 in i3 i1 i0 Left shifter <<1 Symbol inL i3 q3 q2 q1 q0 i2 i1 i0 inR 2 s0 s1 shL shR 1 Shifter with left shift, right shift, and no shift 1 in sh i3 q3 q2 q1 q0 i2 i1 i0 Shifter with left shift or no shift

Counter, Incrementer & Timer

Modularized Counter In the previous chapter we designed counter to just count the clock pulses As a datapath component, counter needs control lines so it can be integrated into a bigger design We will see more modularized counter design as a datapath component Vahid 4.9 pg 215

Modularized Up Counter Regular up counter can be modularized to have Registers to keep count value Incrementer Terminal count detector – for up counter, it is an AND gate as we assume the terminal count is all ones ld 4-bit register C t c 4 n 4-bit up-counter +1 1 c n t C 4-bit up-counter 4 0100 0101 0011 0010 0000 0001 0000 1111 1 0001 1110 ... Vahid pg 216

Incrementer Incrementer is an adder whose job is to always add 1 to its input It is natural to design incrementer using FULL adder setting one of the addend to a constant 1 However, a better design will be using cascaded HALF adders with a 1 addend at LSB This can be done since the second addend is basically zero (except at LSB), hence lifting its need as one of full adder inputs which means we can reduce the full adder to half adder This results in a simpler circuit

Incrementer 0011 + 0001 0011 + 1 + 0000 a3 c o s F A a2 s3 s2 s1 ci b 1 0011 + 0001 equivalent equivalent a3 c o s H A a2 s3 s2 s1 b a a1 s0 a0 1 0011 + 1 + 0000

Modularized Down Counter Modular down counter may have Registers to keep count value Decrementer Terminal count detector – for down counter, it is a NOR gate as we assume the terminal count is all zeros 4-bit down-counter c n t ld 4-bit register 4 4 4 –1 t c C 4

Decrementer Decrementer is a subtractor whose job is to always minus 1 from its input Decrementer can be designed using full adder by setting one of the addend to all 1-s This is true because subtracting by 1 is equivalent to adding with 2’s complement of 1, and 2’s complement of 1 is a binary number with all 1-s There is a way to design decrementer using HALF SUBTRACTOR (HS), but we are not going into detail about it as it is not so behavioral design friendly as HS is not well accepted as datapath component a3 1 a2 1 a1 1 a0 1 a b ci a b ci a b ci a b ci F A F A F A F A c o s c o s c o s c o s c o s3 s2 s1 s0

Up/Down Counter To make it a more useful counter in datapath circuit, we might want to add more control to the counter One possible control is to control the direction counting – either up or down This can be done adding another DIR (direction) control line DIR will be used to multiplex the: feedback input to register – either from incrementer or decrementer terminal count detecter – either from AND or NOR gate

Up/Down Counter 4-bit register C t c 4 dir 4-bit up/down counter –1 +1 2 x 4-bit 2 Vahid pg 217

Timer Timer is just a counter that is clocked by a KNOWN clock frequency Normally it is an up counter, with additional controls of: count (CNT) – only count if CNT is 1 clear (CLR) – synchronously reset timer if CLR is 1 Vahid pg 222

Comparator

Equality Comparator Comparator is a datapath component that test the values of its two inputs for equality, less than or greater condition Equality comparator just test for equality Obviously equality test can be done by comparing the equality of the two inputs bit-by-bit Comparison can be done bit-by-bit by 2-input XNOR gates, then combine the output by an AND Vahid 4.4 pg 191

Equality Comparator Example comparing 0110 to 0111: 1 1 1 1 1 a3 b3 a2 ( a ) b 4-bit equality comparator 1 1 1 1 1

Magnitude Comparator Magnitude comparator gives all possible equality, less than or greater than condition Algorithm to compare A and B starting at MSB: If the bit are the same repeat to compare next LSB Else if bit A is 1 and bit B is 0 then stop by giving condition A > B Else if bit A is 0 and bit B is 1 then stop by giving condition A < B 1011 1001 Equal A=1011 B=1001 So A > B 1011 1001 Equal 1011 1001 Unequal Vahid pg 192

Cascade Comparator From the algorithm in the previous slide, we can formulate one stage of the bit-by-bit comparison using the following circuit: from previous stage a b to next stage out_gt in_gt out_lt in_lt out_eq in_eq

Cascade Comparator At each stage: out_gt = in_gt + (in_eq * a * b) A>B (so far) if already determined in higher stage, or if higher stages equal but in this stage a=1 and b=0 out_lt = in_lt + (in_eq * a * b) A<B (so far) if already determined in higher stage, or if higher stages equal but in this stage a=0 and b=1 out_eq = in_eq * (a XNOR b) A=B (so far) if already determined in higher stage and in this stage a=b too in_gt in_eq in_lt out_gt out_eq out_lt Igt Ieq Ilt Stage 3 a3 b3 a b Stage 2 a2 b2 Stage 1 a1 b1 AgtB AeqB AltB Stage 0 a0 b0

Cascade Comparator Example comparing 1011 to 1001: 1 = 1 1 1 1 a3 b3 1 1 1 a3 b3 a2 b2 a1 b1 a0 b0 a b a b a b a b in_gt out_gt in_gt out_gt in_gt out_gt in_gt out_gt A gtB 1 1 in_eq out_eq in_eq out_eq in_eq out_eq in_eq out_eq A eqB in_lt out_lt in_lt out_lt in_lt out_lt in_lt out_lt A ltB S tage3 S tage2 S tage1 S tage0 ( a ) 1 1 = 1 1 1 a3 b3 a2 b2 a1 b1 a0 b0 a b a b a b a b in_gt out_gt in_gt out_gt in_gt out_gt in_gt out_gt A gtB 1 1 in_eq out_eq in_eq out_eq in_eq out_eq in_eq out_eq A eqB in_lt out_lt in_lt out_lt in_lt out_lt in_lt out_lt A ltB S tage3 S tage2 S tage1 S tage0 ( b )

Cascade Comparator Example comparing 1011 to 1001 (continue): 1 1 1 1 > 1 1 a3 b3 a2 b2 a1 b1 a0 b0 a b a b a b a b 1 in_gt out_gt in_gt out_gt in_gt out_gt in_gt out_gt A gtB 1 in_eq out_eq in_eq out_eq in_eq out_eq in_eq out_eq A eqB in_lt out_lt in_lt out_lt in_lt out_lt in_lt out_lt A ltB S tage3 S tage2 S tage1 S tage0 ( c ) 1 1 1 1 1 a3 b3 a2 b2 a1 b1 a0 b0 a b a b a b a b 1 in_gt out_gt in_gt out_gt in_gt out_gt in_gt out_gt A gtB 1 in_eq out_eq in_eq out_eq in_eq out_eq in_eq out_eq A eqB in_lt out_lt in_lt out_lt in_lt out_lt in_lt out_lt A ltB S tage3 S tage2 S tage1 S tage0 ( d )

Comparator Application Minimum of 2 numbers: MIN Igt Ieq Ilt AgtB AeqB AltB 1 A B 8-bit magnitude comparator s I 2x1 mux 8-bit C 8 M in ( a ) b

Adder, Subtractor & 2’s Complement, Multiplier

Half Adder Half adders add two 1 bit inputs, then generate 1 bit sum and 1 bit carry a b s 1 c b a I nputs O utputs a b Half Adder c s c s Truth Table Block Diagram Circuit

Full Adder Full adders add two 1 bit inputs and one carry-in then generate 1 bit sum and 1 bit carry-out s 1 c o ci b a I nputs O utputs Circuits c o ci b a s Truth Table a b ci Full adder Block Diagram Full Adder co s

Larger Adder – Ripple Carry Arbitrary no. bit adder can be constructed by cascading half adder and full adder as follows: This is called carry ripple technique as the carry is being transferred from one adder to the next one a3 c o s F A b3 a2 b2 s3 s2 s1 ci b a a1 b1 s0 a0 b0 H a3 c o s F A b3 a2 b2 s3 s2 s1 ci b a a1 b1 s0 a0 b0 OR

Cascading Adders a3 a2 a1 a0 b3 s3 s2 s1 s0 c o s7 s6 s5 s4 ci b2 b1 4-bit adder a7.. a0 b7.. b0 s7.. s0 c o ci 8-bit adder

Subtractor sub/add b3 b2 b1 b0 a3 a2 a1 a0 a b ci a b ci a b ci a b ci F A F A F A F A c o s c o s c o s c o s c o s3 s2 s1 s0

2’s Complement 2’s comp circuit can be constructed from the circuit in the previous slide by setting the minuend to 0 (zero) Or the following dedicated 2’s comp circuit can be used: