EE365 - Microprocessors period 26 10/23/00 D. R. Schertz # Parallel Ports

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EE365 - Microprocessors period 26 10/23/00 D. R. Schertz # Parallel Ports

8051 Ports u All four ports on an 8051 contain a latch, an input buffer, and an output buffer. u Reading from the port reads the value of the port pin through the input buffer. u Instructions that read-modify-write read from the latch so that the rewrite will reflect actual latch data.

Ports 1 and 3 u Ports 1 and 3 are used as general purpose ports. u The port 3 pins also have alternate functions used by some of the other peripherals. u In both cases, the ports are quasi-bidirectional, that is, they are output ports with a pulldown transistor and a weak pullup and can be pulled down by an external gate. u This means that a 1 must be written to a bit for that bit to be used as an input.

Ports 0 and 2 u Ports 0 and 2 are used as the external bus when external memory or I/O devices are used. u In this case, port 0 is used for the multiplexed data and low order address. u Port 2 is used for the high order address bits.

Port 2 u Port 2 is the same as ports 1 and 3 when used as a general purpose I/O port. u When it is used as the high order part of the address, it uses a strong pullup when the address bit is a 1. u This gives better rise time response than the weak internal pullup would.

Port 0 u Port 0 is an open collector output when used as a general purpose port. u This means that it can be used as a high impedance input port. u When it is used as the address/data bus, it has a stronger pullup transistor used. u Port 0 has twice the drive in the low state and significantly higher drive in the high state than the other ports.

Input and Output Devices u There are several examples of input and output given in the chapter. –Input dip switch –Output LED indicators –Output 7 segment displays –Input keyboard –Liquid -Crystal display –Digital to Analog converter (later)

8255 Programmable Peripheral Interface u The Intel 8255 is a parallel port peripheral. u It has 3 8-bit ports A, B, and C. u Port C bits can be used to provide handshaking for ports A and B. u Port A, Port B, the upper nybble of Port C, and the lower nybble of Port C can each be independently assigned to be an input or an output port.

8255 Programmable Peripheral Interface u The chip takes standard Intel 8-bit signals as its inputs. u RD’ u WR’ u A1,A0 - select 1 of four internal registers u CS’ - overall chip select u RESET

8255 Programmable Peripheral Interface u The chip has three modes of operation: –Mode 0 - dumb I/O (all ports) –Mode 1 - handshake I/O (ports A and B) –Mode 2 - bidirectional handshake (port A) u In modes 1 and 2, some of the bits of port C are used for the control lines for ports A and B. u The remaining bits of port C are general purpose I/O.

8255 Control Word u There is a control word to program the actions of the chip. u The chip mode is set when bit 7 of the control word has the value 1

8255 Control Word u Data direction is controlled by several bits where 1 indicates input and 0 indicates output: –D0 - Port C lower nybble –D1 - Port B –D3 - Port C upper nybble –D4 - Port A u D2 sets the mode for port B. u D6,D5 set the mode for port A.

8255 Control Word u A second use of the control word is accessed by writing a 0 in bit 7. u In this case, any one bit of port C can be set or reset individually. u Bit 0 of the control word contains the value to be written. u Bits 3,2,1 select the bit position to be written.

8255 Strobed I/O u The examples following are shown for port A. u Those for port B (mode 1 only) are similar.

8255 Strobed Input u The configuration of port C pins for Port A strobed input is: 4 STB’ 5 IBF’ 3 INTR

8255 Strobed Input u The waveforms for the handshake for mode 1 input are:

8255 Strobed Output u The configuration of port C pins for Port A strobed output is: 7 OBF’ 8 ACK’ 3 INTR

8255 Strobed Output u The waveforms for the handshake for mode 1 output are:

8255 Bidirectional Strobed I/O u The operation of mode two for port A basically combines the input and output signals from the two previous slides into one.