1. Lecture 07: 8255 PPI Chip

2. The 80x86 IBM PC and Compatible Computers Chapter 11.4 8255 PPI Chip PPI: Programmable Parallel Interface (so it is an I/O module)

3. Recall in Lecture 02: I/O Module Diagram Data Register Status/Control Register External Device Interface Logic External Device Interface Logic Input Output Logic Data Lines Address Lines control Lines Data Status Control Data Status Control Systems Bus InterfaceExternal Device Interface

4. Package & Internal Structure

5. Internal Structure and Pins zThree data ports: A, B, and C yPort A (PA 0 ~PA 7 ): can be programmed all as input/output yPort B (PB 0 ~PB 7 ): can be programmed all as input/output yPort C (PC 0 ~PC 7 ): can be split into two separate parts PCU and PCL; any bit can be programmed individually zControl register (CR) yInternal register: used to setup the chip zGroup A, Group B and control logic yGroup A (PA & PCU) yGroup B (PB & PCL)

6. Internal Structure and Pins zData bus buffer yAn interface between CPU and 8255 yBidirectional, tri-state, 8-bit zRead/Write control logic yInternal and external control signals yRESET: high-active, clear the control register, all ports are set as input port y~CS, ~RD, ~WR yA 1, A 0 : port selection signals ~CS A 1 A 0 ~RD ~WRFunction 0 0 00 1PA->Data bus 0 0 10 1PB->Data bus 0 1 00 1PC->Data bus 0 0 01 0Data bus->PA 0 0 11 0Data bus->PB 0 1 01 0Data bus->PC 0 1 11 0Data bus->CR 1 × ×1 D 0 ~D 7 in float

7. Operation Modes zInput/output modes yMode 0, simple I/O mode: xPA, PB, PC: PCU{PC 4 ~PC 7 }, PCL{PC 0 ~PC 3 } xNo Handshaking: negotiation between two entities before communication xEach port can be programmed as input/output port yMode 1: xPA, PB can be used as input/output ports with handshaking xPCU{PC 3 ~PC 7 }, PCL{PC 0 ~PC 2 } are used as handshake lines for PA and PB, respectively yMode 2: xOnly PA can be used for bidirectional handshake data transfer xPCU{PC 3 ~PC 7 } are used as handshake lines for PA zBit set/reset (BSR) mode yOnly PC can be used as output port yEach line of PC can be set/reset individually

8. Control Register & Op. Modes zControl Register yA 8-bit internal register in 8255 ySelected when A 1 =1, A 0 =1 yMode selection word xInput/output modes xBSR mode

9. Select Input/output Modes zInput/output modes Group A controlGroup B control

10. Select Input/output Modes zInput/output modes

11. Select Input/output Modes zInput/output modes

12. Select Input/output Mode Examples z1. Write ASM instructions for setting the 8255 in simple I/O mode with PA and PB being output port and PC being input port. z2. Assume that the address of the control register of the 8255 is 63H, give out the instructions that set up the 8255 in mode 0 where PA, PB and PCU are used as input ports and PCL is used as output port.

13. Select BSR Mode zBSR Mode Arbitrary value Indicate which line in PC: 000 – PC 0 001 – PC 1 … 111 – PC 7 0 – Reset 1 – Set

14. Select BSR Mode Examples zAssume PC is used as an output port which connects to 8 LED segments, now turn off the second LED segment with the rest unchanged (e.g., for LED segments in this case, 1-on, 0-off). zUsing BSR mode instead:

15. Select BSR Mode Examples zAssume the address range for a 8255 is 60H~63H, PC 5 is outputting a low level, write code to generate a positive pulse.

16. Mode 0 (Simple I/O) zFor simple input/output scenario yNo handshaking needed yAny port of PA, PB and PC (PCU, PCL) can be programmed as input or output port independently yPCU=PC 4 ~PC 7, PCL=PC 0 ~PC 3 yCPU directly read from or write to a port using IN and OUT instructions yInput data are not latched, Output data are latched yE.g., setting up the control register for Mode 0

17. Mode 0 Example

18. Mode 1 (Strobe I/O) zFor handshake input/output scenario yPA and PB can be used as input or output ports yPCU=PC 3 ~PC 7, used as handshake lines for PA yPCL=PC 0 ~PC 2, used as handshake lines for PB yBoth input and output data are latched

19. Mode 1: As Input Ports zPC 3 ~PC 5 and PC 0 ~PC 2 are used as handshake lines for PA and PB, respectively y~STB: the strobe input signal from input device loads data into the port latch yIBF: Input Buffer Full output signal to the device indicates that the input latch contains information (can also be used for programmed I/O) yINTR: Interrupt request is an output to CPU that requests an interrupts (for interrupted I/O) zPC 6 and PC 7 can be used as separate I/O lines for any purpose zINTE: the interrupt enable signal is neither an input nor an output; it is an internal bit programmed via the PC 4 (port A) or PC 2 (port B); 1-allowed, 0-forbidden

20. Mode 1: As Input Ports zControl register zPC stores all status information Indicates Group A Mode 1 PA: Input PC 6, PC 7 : 1-input 0-output Indicates Group B Mode 1 PB: Input

21. Timing in Mode 1 Input zInput device first puts data on PA 0 ~PA 7, then activates ~STB A, data is latched in Port A; z8255 activates IBF A which indicates the device that the input latch contains information but CPU has not taken it yet. So device cannot send new data until IBF A is cleared; zWhen IBF A, ~STB A and INTE A are all high, 8255 activates INTR A to inform CPU to take data in PA by interruption; zCPU responds to the interruption and read in data from PA; the ~RD signal will clear INTR A signal; zAfter CPU finishes reading data from PA (i.e., ~RD signal goes high), the IBF A signal is cleared.

22. Mode 1: As Output Ports zPC 3, PC 6, PC 7 and PC 0 ~PC 2 are used as handshake lines for PA and PB, respectively y~OBF : Output buffer full is an output signal that indicates the data has been latched in the port y~ACK : The acknowledge input signal indicates that the external device has taken the data yINTR: Interrupt request is an output to CPU that requests an interrupts zPC 4 and PC 5 can be used as separate I/O lines for any purpose zINTE: the interrupt enable signal is neither an input nor an output; it is an internal bit programmed via the PC 6 (port A) or PC 2 (port B); 1-allowed, 0-forbidden

23. Mode 1: As Output Ports zControl register zPC stores all status information Indicates Group A Mode 1 PA: Output PC 4, PC 5 : 1-input 0-output Indicates Group B Mode 1 PB: Output

24. Timing in Mode 1 Output zIf INTR A active, CPU responds to the interruption and writes data to PA and clears the INTR A signal; zWhen data has been latched in PA, 8255 activates ~OBF A which informs the output device to pick up data; zAfter the output device has taken the data, it sends ~ACK A signal to 8255 which indicates that the device has received the data, and also makes ~OBF A go high, indicating CPU can write new data to 8255; zWhen ~OBF A, ~ACK A and INTE A are all high, 8255 sends an INTR A to inform CPU to write new data to PA by interruption.

25. Mode 2 (Bidirectional Bus) zFor bidirectional handshake input/output scenario yOnly PA can be used as both input and output port yPCU=PC 3 ~PC 7, used as handshake lines for PA yBoth input and output data are latched

26. Mode 2: As Input & Output Port zPC 3 ~ PC 7 are used as handshake lines for PA z~OBF A, ~ACK, IBF A, ~STB A, INTR A zPC 0 ~ PC 2 can be used as separate I/O lines for any purpose, or as handshake lines for PB zWhen CPU responds to an interrupt of 8255 working in Mode 2, it has to check the ~OBF A and IBF A in order to tell whether the input process or the output process is generating the interrupt.

27. Mode 2: As Input & Output Port zControl register zPC stores all status information Indicates Group A Mode 2

28. Polling vs. Interruptions zIn Mode 1 and 2, PC stores status of Group A and/or Group B  By reading from PC using IN instruction, you can use polling method to check the state of I/O devices

29. Programming with 8255 zAs shown in the figure, PA and PB of the 8255 are working in mode 0. PA used as input port connects to 4 switches, and PB used as output port connects to a 7-segment LED. Write a program to display a hex digit that the switches can represent.

31. Address Decoding zWhat are the addresses of ports and the control register? zPA : 8020H zPB : ? zPC : ? zCR : ?

32. A Solution Program

34. Experiment 2