1. 8255: Programmable Peripheral Interface (PPI)
8255 is a parallel IO device interface – programmed to transfer data bits simultaneously over equal number of parallel data lines.

2. Construction and pinout diagram
8255 PPI is a 40 pin chip
consists of
Data lines : D7-D (8)
Address lines: A1-A (2)
Control lines: /RD, /WR (2)
Chip select line: /CE (1)
Reset Line: RST (1)
Power lines: VCC, GND (2)
8 bit parallel ports
PA, PB, PC (24)
Total Number of pins

3. Schematic diagram

4. Registers A control register,
Three data registers - corresponding to the ports A, B and C, and
A status register - accessible by reading the port C in handshaking configuration of data I/O.
The three data registers and control register is accessed using the address lines A1-A0.

5. Features of port registers
Ports A & B can be used as 8 bits I/O
Port C is special:

6. Special features of Port C register
Port C can be used as 8 bits I/O
Port C can be used as 4 bits I/O ports- PCU (upper 4 bits of port C) and PCL, (lower 4 bits of port C)
Individual lines of port C can be set or reset, used as switches
Lines of port C are used for handshake signals for ports A & B

7. Internal register addresses

8. Working mode a) IO mode- (data transfer through ports A, B, C)
b) Bit set reset mode [BSR]-(port C bits as switches)

9. In IO mode ports A, B, C are used to input or output data.
The ports are configured by writing an IO mode control word in control register.

10. Types of IO modes
Mode 0 – simple unidirectional data transfer, all ports functions as simple IO port
Mode 1 – unidirectional data transfer with handshaking
Mode 2 – bidirectional data transfer with handshaking

11. Description of IO modes with hand shake
IO mode 1 : IO ports A and B can be setup for uni-directional data transfer using bits from port C as double hand shake signals,
IO mode 2 : Port A can be setup for bi-directional data transfer using double hand shake signals from port C and port B can be setup either in mode 0 or mode 1

12. Format of control word for IO modes
The control word for IO mode is coined by the values of the data bits as per format shown below:
CW_IO = D7 D6 D5 D4 D3 D2 D1 D0

13. Bit Set Reset mode (BSR)
In BSR mode individual bits of port C can be used as on / off switch to control devices.
In this mode each of the eight bits of port C can be selected and set or reset by writing a BSR control word into control register.

14. Format of control word for bit set reset (BSR) mode
The control word for BSR mode is coined by the values of the data bits as per format shown below: CW_BSR = D7 X X X D3 D2 D1 D0

15. Port A uses upper 3 signals PC3, PC4, PC5,
IO mode 1
Port A uses upper 3 signals PC3, PC4, PC5,
Port B uses lower 3 signals PC0, PC1, PC2,
PC6, PC7 are used as input / output.

16. IO mode 1 – input Description and diagram
Port A and B as input
PC6 and PC7 as IO

17. IO mode 1 – input Handshake signals

18. IO mode 1 – input Handshake signals (cont.)
INTE (interrupt enable): This internal flipflop to a port is needed to generate the INTR. The flipflops INTEA and INTEB are controlled by bits PC4 and PC2 through BSR mode.

19. Example: Control word IO mode 1 – input
PCL used for handshake signals

20. Status Word IO mode 1 – input
PC7 PC6
The status word will be copied into the accumulator register if Port C is read in handshaking modes 1 & 2
Bit 5 (/OBFA) and Bit 1 (/OBFB) can be used for data transfer using IO with status check (polling) method.

21. IO mode 1 – output Description and diagram
Port A and B as output
PC4 and PC5 as IO

22. IO mode 1 – Output control signals

23. IO mode 1 – output control signals (cont.)
INTE (interrupt enable): This internal flipflop to a port is needed to generate the INTR. The flipflops INTEA and INTEB are controlled by bits PC6 and PC2 through BSR mode.

24. Example: Control word IO mode 1 – output
PCL used for handshake signals

25. Status Word IO mode 1 – output
PC5 PC4
The status word will be copied into the accumulator register if Port C is read in handshaking modes 1 & 2
Bit 7 (/OBFA) and Bit 1 (/OBFB) can be used for data transfer using IO with status check (polling) method.

26. Mode 2: Bidirectional Data Transfer Configuration of ports
Port A can be configured as bidirectional port
and
b. Port B either in mode 1 (unidirectional ) or
Port B in mode 0 (simple I/O data transfer) and Port C in simple I/O data transfer

27. Mode 2: Handshake lines
Port A uses five bits from port C (PC3-PC7) as handshake signals for data transfer,
Three remaining bits from port C (PC2-PC0) can be used as
simple IO or
handshake for Port B

28. Handshake Signals for Port A - mode 21
INTE1 & INTE2 are enabled by setting PC6 and PC4 in BSR mode. 2

29. Port A Mode 2 and Port B mode 0 (Input)
8255

30. Port A Mode 2 and Port B mode 1 (Output)
8255

31. Mode 2 – Status Word

32. Performing IO with handshake
IO with handshake can be performed based upon
status check I/O or
interrupt I/O.

33. IO with handshake using status check (Polling)
The MPU checks the status word continuously for bits IBF or OBF until
IBF goes high (input with handshake) or
OBF goes low (output with handshake).

34. IO with handshake using Interrupt
INTEA / INTEB is set or reset in the BSR mode,
INTR line is used to implement the interrupt, (connected to the INT, RSTx, TRAP lines of MPU 8085).

35. Programming 8255 a) Preparation
Determine from the circuit whether the PPI is memory mapped or IO mapped.
The 8255 is memory mapped if its
/RD line is connected to /MEMR,
/WR lines is connected to /MEMW of device selector interface
Address is 16bits
Instructions are LDA addr16 & STA addr16

36. Preparation (cont.) The 8255 is IO mapped if its
/RD line is connected to /IOR,
/WR lines is connected to /IOW of device selector interface
Address is 8bits
Instructions are IN addr8 & OUT addr8

37. Preparation (cont.)
Determine the full address of ports A, B, C and control register, (from the address table containing chip select and register select address bits)
Determine the control words (CW) to configure the ports A, B & C, (bit pattern formats)
Input / output control word (IO_CW)
For interrupt based data transfer
Bit set / reset control word (BSR_CW)

38. Programming 8255 b) Write codes
1. Configuration
Write the IO control word into the control register,
Write the BSR control word into the control register, in case if the interrupt lines has to be enabled in IO modes 1 & 2.
2. Data Transfer
Read or write data from / into ports using data transfer instructions and addresses of the ports,
For IO mode 1 & 2 data transfer can be based upon using either status check or interrupt

39. Program Codes 1. Configuration
a. Select I/O mode : Write I/O control word into the control register MVI A, I/O_CW; (I/O_CW -> A -> CR) OUT CR_addr8 ; device is IO mapped (STA CR_addr16 ; device is memory mapped ) I/O with interrupt: b. Enable interrupt: Write BSR control word into the control register MVI A, BSR_CW; (BSR_CW -> A -> CR)

40. Program Codes 2. Data transfer
2.1. Data output : (byte -> A -> DR)
MVI A, abyte8
OUT DR_addr8 ; device is IO mapped
(STA DR_addr16 ; device is memory mapped )
2.2. Data input: (DR -> A)
IN DR_addr8 ; device is IO mapped
(LDA DR_addr16 ; device is memory mapped )
For I/O with interrupt - data transfer instructions are part of Interrupt Service Routine !

41. Example: Addresses of the various registers for the circuit
8255 is IO mapped since its RD⌐, WR⌐ lines are connected to conditioned signal lines IOR⌐, IOW⌐

42. Example: Read a DIP switch from PB and display at PA in IO mode 0
8255 is memory mapped since its RD⌐, WR⌐ lines are connected to conditioned signal lines MEMR⌐, MEMW⌐