V2000 Front End Module architecture MDB TLS March 21, 2006 Gilles Ducas

RF Block Diagram SP3T Transaam Orphee

Scorpius architecture Transaam Orphee

Carina architecture NC Transaam Orphee

FEM Block Diagram

Handover scenarios

Decoder Logic Table

Design key points Timing accuracy: FEM is programmed through 3 GPO’s from A+/ALV trigg’d by a DVI: very low timing accuracy due to interrupts processing delay in the DSP => Latch input (L1T) has been added to achieve required timing accuracy Additional attenuation of the Bluetooth band required in low band path of the diplexer to avoid Bluetooth desense due to 800MHz 3rd harmonic  Spec: 35dB, at the cost of higher insertion loss Return loss on PCS path: Orphee is marginal on PCS max output power. Return loss must be as close as possible to 20dB. Spec is currently 11dB min, should be changed to 18dB min. Intermodulation Product power in RX band (see next slide)

Intermodulation Product Power 1710MHz Calibrated at antenna port Spec: -103dBm to avoid receiver desense, whatever the phase at FEM inputs. Test conditions: Pwr (Ftx) = +20dBm at antenna Pwr (Fint) = -15dBm at antenna (injected from the antenna toward the FEM) Measure IMP power (Frx) at RX output of the FEM Some vendors (NEC, Eudyna) are using a DC-DC converter to increase switches supply voltage, hence improving linearity.

Current drain Current drain reduction: Vdd is a permanent supply from Atlas that can’t be switched off => Shut-off mode to disable the decoder => Target: 30µA max, 20µA typ. FEM wakeup timing (out of DSM): Goal: to wake the FEM up as late as possible to save current. - GSM mode: wakeup 5ms prior to the first RX slot. Could be reduced to 100µs but this is not a priority since current saving is 3µA average in DRX5 (1.12s DSM duty cycle) - WCDMA mode: 248µs prior to first RX DC-DC converter Could slightly increase the active current drain (extra µA). Shut-off mode current should not be impacted.

Eudyna pass#8 design status (1/5)

Eudyna pass#8 design status (2/5) TX paths attenuations

Eudyna pass#8 design status (3/5)

Eudyna pass#8 design status (4/5) Harmonics

Eudyna pass#8 design status (5/5)

Triquint ES4 design status (1/8)

Triquint ES4 design status (2/8)

Triquint ES4 design status (3/8)

Triquint ES4 design status (4/8)

Triquint ES4 design status (5/8)

Triquint ES4 design status (6/8)

Triquint ES4 design status (7/8)

Triquint ES4 design status (8/8)

ParameterFrequency Condition s Spec CEL/NECEPCOSSkyworksMurataTriquintEudyna MaxMax Uni ts DS4NewSample 2 ES4Pass#6 Insertion Loss (1a) GSM850 / GSM900 Tx Pin=+34d Bm, +25°C 1. 3 dB Insertion Loss (1b) WB850 (band V or VI) TxRx Pin=+26d Bm, +25°C 1. 3 dB Insertion Loss (2a) GSM1800 / GSM1900 Tx Pin=+32d Bm, +25°C 1. 4 dB Insertion Loss (2b) WB 2100 (band I) Tx Pin=+26d Bm, +25°C 1. 7 dB ? Insertion Loss (3a) GSM850 Rx Pin=- 15dBm, +25°C 1. 4 dB Insertion Loss (3b) GSM900 Rx Pin=- 15dBm, +25°C 1. 4 dB Insertion Loss (4a) GSM1800 Rx Pin=- 15dBm, +25°C 1. 6 dB Insertion Loss (4b) WB1900 (band II) TxRx / GSM1900 Rx Pin=+26d Bm, +25°C 1. 6 dB IL Average Vendor Ranking CEL/NECEPCOSSkyworksMurataTriquintEudyna Design status (1/7)

Design status (2/7) Worst Case (max level) Vendor Ranking Worst Case (max level) Vendor Ranking NEC Mura ta SkyW orks EPC OS TriQ uint Eud yna NEC Mur ata SkyW orks EPC OS TriQ uint Eud yna

Design status (3/7) ParameterConditionsFrequency Spec CEL/NECEPCOSSkyworksMurataTriquintEudyna MaxUnits DS4NewSample 2 Return Loss At all Tx and antenna port input, +25C 824 – 915 MHz 15dB – 1910 MHz 11dB – 1980 MHz 10dB Average Return Loss Vendor Ranking Return Loss

Design status (4/7) LB path attenuation

Design status (5/7) HB path attenuation

Design status (6/7) NECMurataSkyWorksEPCOSTriQuint IM3 W.C Avg Ranking12534

Design status (7/7) Summary of Vendor Ranking Weighting TriquintEudynaSkyworksNECEpcosMurata Insertion Loss Return Loss nd Harmonic rd Harmonic GSM LB Path Attenuation WCDMA LB Path Attenuation GSM HB Path Attenuation WCDMA HB Path Attenuation IM Average Overall Ranking Not in the Approved Supplier List