CS/EE 3700 : Fundamentals of Digital System Design Chris J. Myers Lecture 5: Arithmetic Circuits Chapter 5 (minus 5.3.4)

Positional Number Representation Decimal: –D = d n-1 d n-2...d 1 d 0 –V(D) = d n-1  10 n-1 + d n-2  10 n d 1  d 0  10 0 Binary: –B = b n-1 b n-2...b 1 b 0 –V(B) = b n-1  2 n-1 + b n-2  2 n b 1  b 0  2 0 (5.1)

Conversion: Binary to/from Decimal Conversion of binary to decimal: use 5.1. –(1101) 2 = Conversion of decimal to binary: –V = b n-1  2 n-1 + b n-2  2 n b 1  b 0 –V/2 = b n-1  2 n-2 + b n-2  2 n b 1 + b 0 /2 –Quotient is: b n-1  2 n-2 + b n-2  2 n b 1 –Remainder is: b 0 –If remainder is 0 then b 0 = 0, if it is 1 then b 0 = 1. –Repeat on quotient to find b 1, etc.

Figure 5.1 Conversion from decimal to binary Convert (857) 10 to binary:

Table 5.1 Numbers in different systems

Conversion: Binary to Oct or Hex ( ) 2 ( ) 2 ( ) 2 ( ) 2

Addition of Unsigned Numbers x + y ---- c s sum carry

Addition of Unsigned Numbers xycs

Figure 5.3 An example of addition (15) 10 (10) 10

Figure 5.4 Full-adder

Use of XOR Gates

Circuit for Full Adder

Figure 5.5 A decomposed implementation of the full-adder circuit HA s c s c c i x i y i c i1+ s i c i x i y i c i1+ s i (a) Block diagram (b) Detailed diagram

Figure 5.6 An n-bit ripple-carry adder FA x n –1 c n c n1” y n1– s n1– FA x 1 c 2 y 1 s 1 c 1 x 0 y 0 s 0 c 0 MSB positionLSB position

Figure5.7 Circuit that multiplies an 8-bit unsigned number by 3

x 1 x 0 y 8 y 0 y 7 x 8 s 0 s 8 c 8 00 a 7 A: P 9 P 8 P 0 P3A= : (b) Efficient design a 0

b n1– b 1 b 0 Magnitude MSB (a) Unsigned number b n1– b 1 b 0 Magnitude Sign (b) Signed number b n2– 0 denotes 1 denotes + –MSB

Sign Magnitude Magnitude of positive and negative numbers represented in same way. Sign used to distinguish them. Simple to understand. Complicates hardware design.

1’s Complement n-bit negative number found by subtracting its positive form from 2 n -1. –K 1 = (2 n – 1) – P Found by just complementing each bit. Examples:

2’s Complement n-bit negative number found by subtracting its positive form from 2 n. –K 2 = 2 n – P –K 2 = K Complement each bit and add 1. Examples:

Sign Magnitude: Add/Sub If both operands have the same sign, then addition is simple. –Add magnitudes and copy the sign. If they have opposite sign, then must subtract smaller from the larger. This is complicated, so sign magnitude not typically used in computers.

Figure 5.9 Examples of 1’s complement addition 2+ () 5–  3-  + 5–  7–  + 2–  5+ () 2+ () 7+ () + 5+ () 3+ () + 2– 

Figure 5.10 Examples of 2’s complement addition 2+ () 5–  3-  + 5–  7–  + 2–  5+ () 2+ () 7+ () + 5+ () 3+ () + 2– 

Figure 5.11 Examples of 2’s complement subtraction 5+ () 2+ () 7+ () – 5+ () 3+ () – 2– 

2+ () 5–  3-  – 5–  7–  – 2– 

Figure 5.12 Graphical interpretation of four-bit 2’s complement numbers – – 3– 4– 5– 6– 7– 8– 0

Figure 5.13 Adder/subtractor unit s 0 s 1 s n1– x 0 x 1 x n1– c n n-bit adder y 0 y 1 y n1– c 0 Add  Sub control

Figure 5.14 Examples of determination of overflow 7+ () 2+ () 9+ () + 7+ () 5 + () + 2–  2+ () 7–  5–  + 7–  9–  +2– 

Detecting Overflow Overflow = c 3 c 4 ’ + c 3 ’c 4 = c 3  c 4 For n-bit numbers, Overflow = c n-1  c n

Performance Issues Price/performance ratio is important. Speed of addition/subtraction has impact on overall speed of a microprocessor. Worst-case delay of a ripple carry adder is: –n  t –Assume  t = 2 gate delays and xor = 1. –Total delay = 2n + 1 gate delays. Must reduce critical path delay.

Carry-Lookahead Adder Must determine carry quickly. –c i+1 = x i y i + x i c i + y i c i –c i+1 = x i y i + (x i + y i )c i –c i+1 = g i + p i c i where g i = x i y i (generate) p i = x i + y i (propagate) –c i+1 = g i + p i (g i-1 + p i-1 c i-1 ) –c i+1 = g i + p i g i-1 + p i p i-1 c i-1 –c i+1 = g i + p i g i-1 + p i p i-1 g i p i p i-1...p 1 g 0 + p i p i-1...p 0 c 0

x 1 y 1 g 1 p 1 s 1 Stage 1 x 0 y 0 g 0 p 0 s 0 Stage 0 c 0 c 1 c 2 Figure 5.15 A ripple-carry adder with generate/propagate signals

Figure 5.16 The first two stages of a carry-lookahead adder x 1 y 1 g 1 p 1 s 1 x 0 y 0 s 0 c 2 x 0 y 0 c 0 c 1 g 0 p 0

High Fan-in Issues c 1 = g 0 + p 0 c 0 c 2 = g 1 + p 1 g 0 + p 1 p 0 c 0... c 8 = g 7 + p 7 g 6 + p 7 p 6 g 5 + p 7 p 6 p 5 g 4 + p 7 p 6 p 5 p 4 g 3 + p 7 p 6 p 5 p 4 p 3 g 2 + p 7 p 6 p 5 p 4 p 3 p 2 g 1 + p 7 p 6 p 5 p 4 p 3 p 2 p 1 g 0 + p 7 p 6 p 5 p 4 p 3 p 2 p 1 p 0 c 0 c 8 = (g 7 + p 7 g 6 + p 7 p 6 g 5 + p 7 p 6 p 5 g 4 ) + [(p 7 p 6 p 5 p 4 )(g 3 + p 3 g 2 + p 3 p 2 g 1 + p 3 p 2 p 1 g 0 ) + (p 7 p 6 p 5 p 4 )(p 3 p 2 p 1 p 0 )c 0

Figure 5.17 A hierarchical carry-lookahead adder with ripple-carry between blocks Block x 3124– c 32 c 24 y 3124– s 3124– x 158– c 16 y 158– s 8– c 8 x 70– y 70– s 70– c 0 3 Block 1 0

Group Propagate/Generate c 8 = g 7 + p 7 g 6 + p 7 p 6 g 5 + p 7 p 6 p 5 g 4 + p 7 p 6 p 5 p 4 g 3 + p 7 p 6 p 5 p 4 p 3 g 2 + p 7 p 6 p 5 p 4 p 3 p 2 g 1 + p 7 p 6 p 5 p 4 p 3 p 2 p 1 g 0 + p 7 p 6 p 5 p 4 p 3 p 2 p 1 p 0 c 0 P 0 = p 7 p 6 p 5 p 4 p 3 p 2 p 1 p 0 G 0 = g 7 + p 7 g p 7 p 6 p 5 p 4 p 3 p 2 p 1 g 0 c 8 = G 0 + P 0 c 0 c 16 = G 1 + P 1 G 0 + P 1 P 0 c 0 c 24 = G 2 + P 2 G 1 + P 2 P 1 G 0 + P 2 P 1 P 0 c 0 c 32 = G 3 + P 3 G 2 + P 3 P 2 G 1 + P 3 P 2 P 1 G 0 + P 3 P 2 P 1 P 0 c 0

Figure 5.18 A hierarchical carry-lookahead adder Block x 158– y 8– x 70– y 70– 3 Block 1 0 Second-level lookahead c 0 s 70– P 0 G 0 P 1 G 1 P 3 G 3 s 158– s 3124– c 8 c 16 c 32 x 3124– y 3124– c

Figure 5.19 An alternative design for a carry-lookahead adder x 1 y 1 g 1 p 1 s 1 s 0 c 2 x 0 y 0 c 0 c 1 g 0 p 0

Figure 5.20 Schematic using an LPM adder/subtractor module

Figure 5.21 Simulation results for the LPM adder Optimized for cost Optimized for speed

Figure 5.23 VHDL code for the full-adder LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY fulladd IS PORT (Cin, x, y: IN STD_LOGIC ; s, Cout: OUT STD_LOGIC ) ; END fulladd ; ARCHITECTURE LogicFunc OF fulladd IS BEGIN s <= x XOR y XOR Cin ; Cout <= (x AND y) OR (Cin AND x) OR (Cin AND y) ; END LogicFunc ;

Figure 5.24 VHDL code for a four-bit adder LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY adder4 IS PORT (Cin: IN STD_LOGIC ; x3, x2, x1, x0 : IN STD_LOGIC ; y3, y2, y1, y0 : IN STD_LOGIC ; s3, s2, s1, s0 : OUT STD_LOGIC ; Cout : OUT STD_LOGIC ) ; END adder4 ; ARCHITECTURE Structure OF adder4 IS SIGNAL c1, c2, c3 : STD_LOGIC ; COMPONENT fulladd PORT ( Cin, x, y : IN STD_LOGIC ; s, Cout : OUT STD_LOGIC ) ; END COMPONENT ; BEGIN stage0: fulladd PORT MAP ( Cin, x0, y0, s0, c1 ) ; stage1: fulladd PORT MAP ( c1, x1, y1, s1, c2 ) ; stage2: fulladd PORT MAP ( c2, x2, y2, s2, c3 ) ; stage3: fulladd PORT MAP ( Cin => c3, Cout => Cout, x => x3, y => y3, s => s3 ) ; END Structure ;

Figure 5.25 Declaration of a package LIBRARY ieee ; USE ieee.std_logic_1164.all ; PACKAGE fulladd_package IS COMPONENT fulladd PORT ( Cin, x, y : IN STD_LOGIC ; s, Cout : OUT STD_LOGIC ) ; END COMPONENT ; END fulladd_package ;

Figure 5.26 Using a package for the four-bit adder LIBRARY ieee ; USE ieee.std_logic_1164.all ; USE work.fulladd_package.all ; ENTITY adder4 IS PORT ( Cin : IN STD_LOGIC ; x3, x2, x1, x0 : IN STD_LOGIC ; y3, y2, y1, y0 : IN STD_LOGIC ; s3, s2, s1, s0 : OUT STD_LOGIC ; Cout : OUT STD_LOGIC ) ; END adder4 ; ARCHITECTURE Structure OF adder4 IS SIGNAL c1, c2, c3 : STD_LOGIC ; BEGIN stage0: fulladd PORT MAP ( Cin, x0, y0, s0, c1 ) ; stage1: fulladd PORT MAP ( c1, x1, y1, s1, c2 ) ; stage2: fulladd PORT MAP ( c2, x2, y2, s2, c3 ) ; stage3: fulladd PORT MAP ( Cin => c3, Cout => Cout, x => x3, y => y3, s => s3 ) ; END Structure ;

STD_LOGIC_VECTOR’s SIGNAL C : STD_LOGIC_VECTOR(1 TO 3); C <= “100” equivalent to: –C(1) = ‘1’, C(2) = ‘0’, C(3) = ‘0’ SIGNAL X : STD_LOGIC_VECTOR(3 DOWNTO 0); X <= “1100” equivalent to: –X(3) = ‘1’, X(2) = ‘1’, X(1) = ‘0’, X(0) = ‘0’

Figure 5.27 A four-bit adder defined using multibit signals LIBRARY ieee ; USE ieee.std_logic_1164.all ; USE work.fulladd_package.all ; ENTITY adder4 IS PORT ( Cin : IN STD_LOGIC ; X, Y : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ; S : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ; Cout : OUT STD_LOGIC ) ; END adder4 ; ARCHITECTURE Structure OF adder4 IS SIGNAL C : STD_LOGIC_VECTOR(1 TO 3) ; BEGIN stage0: fulladd PORT MAP ( Cin, X(0), Y(0), S(0), C(1) ) ; stage1: fulladd PORT MAP ( C(1), X(1), Y(1), S(1), C(2) ) ; stage2: fulladd PORT MAP ( C(2), X(2), Y(2), S(2), C(3) ) ; stage3: fulladd PORT MAP ( C(3), X(3), Y(3), S(3), Cout ) ; END Structure ;

Arithmetic Packages std_logic_signed package defines signed arithmetic for std_logic type. std_logic_unsigned package defines unsigned arithmetic for std_logic type. These are built on top of the package std_logic_arith.

Figure 5.28 VHDL code for a 16-bit adder LIBRARY ieee ; USE ieee.std_logic_1164.all ; USE ieee.std_logic_signed.all ; ENTITY adder16 IS PORT ( X, Y: IN STD_LOGIC_VECTOR(15 DOWNTO 0) ; S : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) ) ; END adder16 ; ARCHITECTURE Behavior OF adder16 IS BEGIN S <= X + Y ; END Behavior ;

Figure 5.29 A 16-bit adder with carry and overflow LIBRARY ieee ; USE ieee.std_logic_1164.all ; USE ieee.std_logic_signed.all ; ENTITY adder16 IS PORT ( Cin : IN STD_LOGIC ; X, Y : IN STD_LOGIC_VECTOR(15 DOWNTO 0) ; S : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) ; Cout, Overflow: OUT STD_LOGIC ) ; END adder16 ; ARCHITECTURE Behavior OF adder16 IS SIGNAL Sum : STD_LOGIC_VECTOR(16 DOWNTO 0) ; BEGIN Sum <= ('0' & X) + Y + Cin ; S <= Sum(15 DOWNTO 0) ; Cout <= Sum(16) ; Overflow <= Sum(16) XOR X(15) XOR Y(15) XOR Sum(15) ; END Behavior ;

Figure 5.30 Use of the arithmetic package LIBRARY ieee ; USE ieee.std_logic_1164.all ; USE ieee.std_logic_arith.all ; ENTITY adder16 IS PORT (Cin : IN STD_LOGIC ; X, Y : IN SIGNED(15 DOWNTO 0) ; S : OUT SIGNED(15 DOWNTO 0) ; Cout, Overflow : OUT STD_LOGIC ) ; END adder16 ; ARCHITECTURE Behavior OF adder16 IS SIGNAL Sum : SIGNED(16 DOWNTO 0) ; BEGIN Sum <= ('0' & X) + Y + Cin ; S <= Sum(15 DOWNTO 0) ; Cout <= Sum(16) ; Overflow <= Sum(16) XOR X(15) XOR Y(15) XOR Sum(15) ; END Behavior ;

Figure 5.31 A 16-bit adder using INTEGER signals ENTITY adder16 IS PORT (X, Y: ININTEGER RANGE TO ; S : OUT INTEGER RANGE TO ) ; END adder16 ; ARCHITECTURE Behavior OF adder16 IS BEGIN S <= X + Y ; END Behavior ;

Multiplication Binary number can be multiplied by 2 shifting it one position to the left: –B = b n-1 b n-2... b 1 b 0 –2  B = b n-1 b n-2... b 1 b 0 0 Similarly, multiplying by 2 k can be done by shifting left by k bit positions. Right shifts divide by powers of 2.

Figure 5.32 Multiplication of unsigned numbers  Multiplicand M Multiplier Q (14) (11) (a) Multiplication by hand

 Multiplicand M Multiplier Q Product P (11) (14) Partial product 0 Partial product 1 Partial product 2 (b) Multiplication for implementation in hardware

Array Multiplier M = m 3 m 2 m 1 m 0 and Q = q 3 q 2 q 1 q 0 Partial product 0: –PP0 = m 3 q 0 m 2 q 0 m 1 q 0 m 0 q 0 Partial product 1: PP0: 0pp0 3 pp0 2 pp0 1 pp0 0 +m 3 q 1 m 2 q 1 m1q 1 m 0 q PP1:pp1 4 pp1 3 pp1 2 pp1 1 pp1 0

Figure 5.33 A 4 x 4 multiplier circuit

Multiplicand M Multiplier Q Product P (+14) (+11) (+154) Partial product 0 Partial product 1 Partial product 2 Partial product 3 (a) Positive multiplicand x

Multiplicand M Multiplier Q Product P (–14) (+11) (–154) Partial product 0 Partial product 1 Partial product 2 Partial product 3 (a) Negative multiplicand x

Fixed-Point Numbers A fixed-point number consists of an integer and fraction part. –B = b n-1 b n-2...b 1 b 0. b -1 b -2...b -k –V(B) = The position of the radix point is fixed. Circuits for fixed point same as integer.

Floating-Point Numbers Fixed-point numbers range limited by the number of significant digits. Floating-point numbers needed to represent very large or very small numbers. –Mantissa  R Exponent Numbers are normalized such that radix point placed to right of first nonzero digit.

Figure 5.35 IEEE standard floating-point formats Sign 32 bits 23 bits of mantissa excess-127 exponent 8-bit 52 bits of mantissa11-bit excess-1023 exponent 64 bits Sign SM SM (a) Single precision (c) Double precision E + E 0 denotes – 1 denotes

Table 5.3 Binary-coded decimal digits

Figure 5.36 Addition of BCD digits X Y Z carry X Y Z carry S = 2 S = 7

BCD Addition Z = X + Y If Z <= 9 then S = Z and carry-out = 0 If Z > 9 then S = Z + 6 and carry-out = 1

Figure 5.37 Block diagram for a one-digit BCD adder

Figure 5.38 VHDL code for a one-digit BCD adder LIBRARY ieee ; USE ieee.std_logic_1164.all ; USE ieee.std_logic_unsigned.all ; ENTITY BCD IS PORT (X, Y : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ; S : OUT STD_LOGIC_VECTOR(4 DOWNTO 0) ) ; END BCD ; ARCHITECTURE Behavior OF BCD IS SIGNAL Z : STD_LOGIC_VECTOR(4 DOWNTO 0) ; SIGNAL Adjust : STD_LOGIC ; BEGIN Z <= ('0' & X) + Y ; Adjust 9 ELSE '0' ; S <= Z WHEN (Adjust = '0') ELSE Z + 6 ; END Behavior ;

Figure 5.39 Functional simulation of the one-digit BCD adder

Figure 5.40 Circuit for a one-digit BCD adder c out Four-bit adder Two-bit adder s 3 s 2 s 1 s 0 z 3 z 2 z 1 z 0 x 3 x 2 x 1 x 0 y 3 y 2 y 1 y 0 c in

Table 5.4 The seven-bit ASCII code

Parity Parity widely used for error-checking. Data transmitted over long wires may be corrupted during transit. Extra parity bit p is added to detect an error. Even parity: p set to make number of 1’s even. –p = x 3  x 2  x 1  x 0 –c = p  x 3  x 2  x 1  x 0 Odd parity: p set to make number of 1’s odd.

Summary Positional number representation. Addition of unsigned/signed numbers. Carry-Lookahead adder. Arithmetic circuit design using VHDL. Multiplication. Other number representations.