Digital Design with VHDL Presented by: Amir Masoud Gharehbaghi

Concurrent Statements Concurrent Signal Assignment Component Instantiation Statement Generate Statement Process Statement Block Statement Concurrent Procedure Call Statement Concurrent Assert Statement

Generate Statement Useful for Modeling Iterative Hardware label: generation_scheme GENERATE BEGIN concurrent statements END GENERATE ; generation_scheme ::= FOR identifier IN range | IF condition

4 bit Ripple Carry Adder (Entity) ENTITY RCA4 IS PORT(a, b: IN BIT_VECTOR(3 DOWNTO 0); cin: IN BIT; z: OUT BIT_VECTOR(3 DOWNTO 0); cout: OUT BIT); END RCA4;

4 bit Ripple Carry Adder (Arch.) ARCHITECTURE iterative OF RCA4 IS SIGNAL cm: BIT_VECTOR(0 TO 3); BEGIN g_main: FOR k IN 0 TO 3 GENERATE g_first: IF k = 0 GENERATE c0: FA PORT MAP (a(k),b(k), cin, z(k), cm(k)); END GENERATE; g_other: IF k > 0 GENERATE co: FA PORT MAP (a(k), b(k), cm(k-1), z(k), cm(k)); END GENERATE; cout <= cm(3); END iterative;

4 bit Ripple Carry Adder (Another) ARCHITECTURE regular OF RCA4 IS SIGNAL cm: BIT_VECTOR(0 TO 4); BEGIN cm(0) <= cin; g_main: FOR k IN 0 TO 3 GENERATE co: FA PORT MAP (a(k), b(k), cm(k), z(k), cm(k+1)); END GENERATE; cout <= cm(4); END regular;

Process Statement PROCESS [ (sensitivity_list) ] [ process_declarative_part ] BEGIN sequential statements END PROCESS ;

Sequential Statements Signal Assignment Statement Variable Assignment Statement IF Statement Case Statement Loop Statement Wait Statement Procedure Call Statement

Sequential Statements (cont.) Next Statement Exit Statement Return Statement Assertion Statement Report Statement Null Statement

Process Example 1 -- an infinite process PROCESS BEGIN x <= ‘ 0 ’, a AFTER 10 ns, b AFTER 35 ns; y <= a AND b AFTER 15 ns; END PROCESS;

Process Example 2 PROCESS (a, b) BEGIN x <= ‘ 0 ’, a AFTER 10 ns, b AFTER 35 ns; y <= a AND b AFTER 15 ns; END PROCESS; -- x <= ‘ 0 ’, a AFTER 10 ns, b AFTER 35 ns; -- y <= a AND b AFTER 15 ns;

Assignment Statements Signal Assignment Statement: target <= waveform ; Variable Assignment Statement: target := expression ;

Process Example 3 PROCESS (a, b) VARIABLE v : INTEGER := 10; BEGIN v := v + a * b; v := 2 * v; c <= v; END PROCESS;

Positive Edge Triggered D-FF PROCESS (clk) BEGIN IF (clk ’ EVENT AND clk = ‘ 1 ’ ) q <= d; END IF; END PROCESS; q_bar <= NOT q;

IF Statement IF condition THEN sequential statements { ELSIF condition THEN sequential statements } [ ELSE sequential statements ] END IF ;

D-FF w/ Asynchronous Set & Reset PROCESS (clk, set, reset) BEGIN IF reset = ‘ 1 ’ THEN d <= ‘ 0 ’ ; ELSIF set = ‘ 1 ’ THEN d <= ‘ 1 ’ ; ELSIF clk ’ EVENT AND clk = ‘ 1 ’ THEN q <= d; END IF; END PROCESS; q_bar <= NOT q;

VHDL Signal Attributes Signal Attributes –‘ EVENT:valueboolean –‘ STABLE [ (time) ]signalboolean –‘ TRANSACTIONsignalbit –‘ LAST_EVENTvaluetime –‘ LAST_VALUEvaluesame type –‘ DELAYED [ (time) ]signalsame type – …

VHDL Array Attributes Array Attributes: –‘ LEFT:left bound –‘ RIGHT:right bound –‘ LENGTH:length –‘ RANGE:range –‘ REVERSE_RANGE:reverse range – …

Register (Entity) ENTITY Reg IS PORT (d: IN BIT_VECTOR; clk, reset: IN BIT; q: OUT BIT_VECTOR); END Reg;

Register (Architecture) ARCHITECTURE general OF Reg IS BEGIN PROCESS(clk, reset) VARIABLE state : BIT_VECTOR(d'RANGE); BEGIN IF (reset = '1') THENstate := (OTHERS => '0'); ELSIF (clk'EVENT AND clk = '0') THEN state := d; END IF; q <= state; END PROCESS; END general;

Aggregate & Concatenation SIGNAL a, b : BIT_VECTOR(3 DOWNTO 0) a <= (b(0), '1', '0', '1'); a '0', 3 => b(0), OTHERS=>'1'); a <= b(0) & b(3 DOWNTO 1);

Case Statement CASE expression IS case_statement_alternative { case_statement_alternative } END CASE ; case_statement_alternative ::= WHEN choices => sequential statements

Mux 4:1 ARCHITECTURE behavioral OF Mux4x1 IS BEGIN PROCESS (a, sel) BEGIN CASE sel IS WHEN “ 00 ” => z <= a(0); WHEN “ 10 ” => z <= a(1); WHEN “ 01 ” => z <= a(2); WHEN “ 11 ” => z <= a(3); -- WHEN OTHERS => z <= a(3); END CASE; END PROCESS; END behavioral;

Loop Statement Iteration_scheme LOOP sequential statements END LOOP; iteration_scheme ::= WHILE condition | FOR identifier IN range

Binary to Integer PROCESS (bin_sig) VARIABLE k: INTEGER := 0; BEGIN k := 0; FOR cnt IN bin_sig ’ RANGE LOOP k := 2*k; IF bin_sig(cnt) = ‘ 1 ’ THEN k := k + 1; END IF; END LOOP; int_sig <= k; END PROCESS;

Integer to Binary PROCESS (int_sig) VARIABLE bin: BIT_VECTOR(bin_sig ’ RANGE); VARIABLE int, k: INTEGER; BEGIN bin := (OTHERS => ‘ 0 ’ ); int := int_sig; k := 0; WHILE int /= 0 LOOP IF int REM 2 = 1 THEN bin(k) := ‘ 1 ’ ; END IF; int := int MOD 2; k := k + 1; END LOOP; bin_sig <= bin; END PROCESS;

Wait Statement WAIT [sensitivity_clause] [condition_clause] [timeout_clause] ; sensitivity_clause ::= ON sensitivity_list condition_clause ::= UNTIL condition timeout_clause ::= FOR time_expression

Wait Examples WAIT;-- wait forever WAIT FOR 0 ns;-- wait a delat time WAIT FOR 10 us; WAIT ON a, b, c; WAIT UNTIL a_sig AND b_var = ‘ 1 ’ ; WAIT ON a_sig UNTIL a_sig AND b_var = ‘ 1 ’ ;