Network Coprocessor (NETCP) Overview

Slides:

Advertisements

Similar presentations

C6614/6612 Memory System MPBU Application Team.

Advertisements

KeyStone C66x CorePac Overview

Yaron Doweck Yael Einziger Supervisor: Mike Sumszyk Spring 2011 Semester Project.

TI Keystone Networking Coprocessor Introduction

Extended Memory Controller and the MPAX registers And Cache

KeyStone Advance Debug

Multicore Applications Team

Multicore Applications

Jaringan Informasi Pengantar Sistem Terdistribusi oleh Ir. Risanuri Hidayat, M.Sc.

A First Example: The Bump in the Wire A First Example: The Bump in the Wire 9/ INF5061: Multimedia data communication using network processors.

Multicore Applications Team KeyStone C66x Multicore SoC Overview.

KeyStone Training Multicore Navigator Overview. Overview Agenda What is Navigator? – Definition – Architecture – Queue Manager Sub-System (QMSS) – Packet.

Keystone PCIe Usage Eric Ding.

KeyStone Training Multicore Applications Literature Number: SPRPXXX

Introduction to K2E Devices

Ethernet Bomber Ethernet Packet Generator for network analysis Oren Novitzky & Rony Setter Advisor: Mony Orbach Started: Spring 2008 Part A final Presentation.

Ethernet Bomber Ethernet Packet Generator for network analysis Oren Novitzky & Rony Setter Advisor: Mony Orbach Spring 2008 – Winter 2009 Midterm Presentation.

Using Multicore Navigator Multicore Applications.

TM Freescale Semiconductor Confidential and Proprietary Information. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc.

Keystone PCIe Usage Eric Ding.

Multicore Software Development Kit (MCSDK) Training Introduction to the MCSDK.

Multicore Navigator: Queue Manager Subsystem (QMSS)

KeyStone 1 + ARM device memory System MPBU Application team.

Multicore Software Development Kit (MCSDK) Training Introduction to the MCSDK.

Using Multicore Navigator

KeyStone Resource Manager June What is resource manager? LLD for global Resource management – static assignment of the device resources to DSP cores.

KeyStone Multicore Navigator

MMI Applications Team October 2011 KeyStone C66x Multicore SoC Overview.

ECE 424 Embedded Systems Design Networking Connectivity Chapter 12 Ning Weng.

TI Accelerates Femtocell Deployments with DSP Solution Kathy Brown General Manager, Wireless Infrastructure Josef Alt Business Development Manager, Communication.

Network Coprocessor (NETCP) Packet Accelerator (PA)

KeyStone Training Network Coprocessor (NETCP) Overview.

Extended Memory Controller and the MPAX registers

KeyStone Training Serial RapidIO (SRIO) Subsystem.

Lecture 3 Review of Internet Protocols Transport Layer.

Introduction to Packet Accelerator (PA). Communication Models Network Access Ethernet ARP FDDI Internet IP Host-to-Host TCP UDP Application TELNET FTP.

C66x KeyStone Training HyperLink. Agenda 1.HyperLink Overview 2.Address Translation 3.Configuration 4.Example and Demo.

RiceNIC: A Reconfigurable and Programmable Gigabit Network Interface Card Jeff Shafer, Dr. Scott Rixner Rice Computer Architecture:

Network Coprocessor (NETCP) Packet Accelerator (PA)

QMSS: Components Overview Major HW components of the QMSS: Queue Manager Two PDSPs (Packed Data Structure Processors): – Descriptor Accumulation / Queue.

C66x KeyStone Training HyperLink

Extended Memory Controller and the MPAX registers And Cache Multicore programming and Applications February 19, 2013.

Keystone PCIe Usage Eric Ding.

Multicore Applications Team

KeyStone Training Multicore Navigator: Packet DMA (PKTDMA)

Keystone Family PCIE Eric Ding. TI Information – Selective Disclosure Agenda PCIE Overview Address Translation Configuration PCIE boot demo.

MMI Applications Team October 2011 KeyStone C66x Multicore SoC Overview.

Chapter 2 Dissecting the OSI Model

Boot Sequence, Internal Component & Cisco 3 Layer Model 1.

XStream: Rapid Generation of Custom Processors for ASIC Designs Binu Mathew * ASIC: Application Specific Integrated Circuit.

Multicore Applications Team KeyStone C66x Multicore SoC Overview.

KeyStone SoC Training SRIO Demo: Board-to-Board Multicore Application Team.

Keystone Advanced Debug. Agenda Debug Architecture Overview Advanced Event Triggering DSP Core Trace System Trace Application Embedded Debug Support Multicore.

NetCP - NWAL API Flow. NetCP (HW,SW) Overview NWAL Feature Overview Data path offload Control configuration –Blocking / Non Blocking support –L2: MAC.

Using Multicore Navigator CIV Application Team January 2012.

1 Chapter 4. Protocols and the TCP/IP Suite Wen-Shyang Hwang KUAS EE.

Slide #1 CIT 380: Securing Computer Systems TCP/IP.

Ethernet Bomber Ethernet Packet Generator for network analysis

Virtual Private Networks Ed Wagner CS Overview Introduction Types of VPNs Encrypting and Tunneling Pro/Cons the VPNs Conclusion.

Quiz 1 Key 3. Class B 5. |Ethernet Frame|IP Datagram|TCP Header|FTP Header|Data|

The OSI Model An ISO (International standard Organization) that covers all aspects of network communications is the Open System Interconnection (OSI) model.

KeyStone SoC Training SRIO Demo: Board-to-Board Multicore Application Team.

The OSI Model. Understanding the OSI Model In early 1980s, manufacturers began to standardize networking so that networks from different manufacturers.

Introduction and Overview of Network and Telecommunications.

The World Leader in High Performance Signal Processing Solutions Heterogeneous Multicore for blackfin implementation Open Platform Solutions Steven Miao.

Ken Gunnells, Ph.D. - Networking Paul Crigler - Programming

SDK for developing High Performance Computing Applications

Digital Signal Processors-1

KeyStone Training Multicore Applications Literature Number: SPRPXXX

Class 3: Embedded TCP/IP Concepts

Presentation transcript:

Network Coprocessor (NETCP) Overview

Agenda What is NETCP? Purpose of the NETCP NETCP Block Diagram Internet Protocol Classification Levels Communication with the NETCP

NETCP Subsystem Overview What is NETCP? Purpose of the NETCP NETCP Block Diagram Internet Protocol Classification Levels Communication with the NETCP 3

What is the Network Coprocessor (NETCP)? 1 to 8 Cores @ up to 1.25 GHz MSMC MSM SRAM 64-Bit DDR3 EMIF Application-Specific Coprocessors Power Management Debug & Trace Boot ROM Semaphore Memory Subsystem S R I O x4 P C e x2 U A T p l i c a t o n - f / 2 Packet DMA Multicore Navigator Queue Manager h r s x3 Network Coprocessor w E G M Accelerator Security PLL EDMA C66x™ CorePac L1 P-Cache D-Cache L2 Cache HyperLink TeraNet Network Coprocessor consists of the following modules: Packet Accelerator (PA) Security Accelerator (SA) Ethernet Subsystem Packet DMA (PKTDMA) Controller

Purpose of the Network Coprocessor Motivation behind NETCP: Use hardware accelerators to do L2, L3, and L4 processing and encryption that was previously required to be done in software Goals for both Packet Accelerator and Security Accelerator: Offload DSP processing power Improve system integration Allow cost savings at the system level Expand DSP usability within current products Allow DSP usage in new product areas Security Key applications: IPSec tunnel endpoint (e.g. LTE eNB, ...) Secure RTP (SRTP) between gateways Air interface (3GPP, Wimax) security processing 5

NETCP Block Diagram . : 32-bit VBUSP TeraNet SCR Config 32-bits 32-bit VBUSP TeraNet SCR CPU/3 CFG TeraNet SCR PKTDMA Controller PKTDMA Controller Pass 1 LUT PDSP+ 1 Timer16 1 PKTDMA_VBUSM_TXRX 128 bits CDE Timer16 2 Pass 1 LUT PDSP+ 2 32-bit VBUSP TeraNet SCR Streaming Interface Switch Timer16 3 CPU/3 Main TeraNet SCR CDE Timer16 4 Pass 1 LUT PDSP+ 3 Timer16 5 CP_ACE Security Unit CP_ACE Security Unit CDE Timer16 6 Pass 2 LUT PDSP+ 4 CDE PDSP Scratchpad RAM 1 PDSP+ 5 PDSP Scratchpad RAM 2 Switch Status INTS CDE . : PDSP+ 6 3-Port Ethernet Switch SGMII 0 SERDES CPSGMII CDE PDSP Scratchpad RAM n SGMII 1 SERDES CPSGMII CPMDIO MDIO 0 INTS PA Stats INTD

Packet DMA in NETCP . . . FFTC (B) Queue Manager Subsystem SRIO FFTC (A) Queue Manager PKTDMA 1 PKTDMA 2 PKTDMA 3 4 . 5 . . 8192 AIF PKTDMA Network Coprocessor PKTDMA PKTDMA NEW

Internet Protocol Classification Layers Layer 2 (L2): Media Access Control (MAC) Layer IEEE 802.3 standard Layer 3 (L3): Internet Layer Internet Protocol Version 4 (IPv4) Internet Protocol Version 6 (IPv6) Custom L3 Classification Layer 4 (L4): Transport Layer User Datagram Protocol (UDP) Transmission Control Protocol (TCP) Custom L4 Classification So now let’s give an overview of the packet classification layers supported by the packet accelerator. The packet accelerator uses provides the ability to classify packets based on Layer 2, Layer 3, and Layer 4 packet headers. Layer 2, the MAC layer, refers to MAC, VLAN, LLC snap headers. Layer 3, the IP layer, refers to IP headers, such as IPv4 or IPv6. Layer 4, the transport layer, refers to udp, tcp, or other layer 4 headers Example Packet L2 L3 L4 Data MAC IPv4 UDP Payload

Communication with the NETCP NETCP relies on QMSS and PKTDMA to communicate with the CorePac. TX Queue Mapping Q640: PDSP1 Q641: PDSP2 Q642: PDSP3 Q643: PDSP4 Q644: PDSP5 Q645: PDSP6 Q646: SASS0 Q647: SASS1 Q648: Switch RX Queues Can use any general purpose queues (Q864-Q8191) Can also use other special purpose queues (e.g. 704-735) PKTDMA TX channels mapped to QMSS PA TX queues Lets discuss how to use the Multicore navigator to communicate with the network coprocessor. Lets begin with transmitting data to the network coprocessor. To transmit data to the network coprocessor, queues 640 through 648 must be used. Each of these queues is mapped to a particular PKTDMA channel, and corresponds to a specific location in the NETCP. For receive, any of the 8192 queues can be used. For communication with the host, the general purpose queues or the high or low priority accumulation queues will probably be used. Unlike the transmit queues, the packet dma receive channels are not tied to a specific queue.

For More Information For more information, refer to the Network Coprocessor (NETCP) User Guide. http://www.ti.com/lit/SPRUGZ6 For questions regarding topics covered in this training, visit the support forums at the TI E2E Community website.