Sean Mathews, Christopher Kiser, Haoxiang Chen

Processor Design Tradeoffs: Instruction Set Design Support useful functions while implementing as efficiently as possible Support equally efficient future implementations Goal is a good compile target, rather than something to be written by the programmer manually

What do processors do? Mostly moving information, less arithmetic operations Because of this, the most important optimizations affect data movement. How can we make them go faster?

Pipelining Most instructions only use a fraction of the processor at any given moment Pipelining is when you start an instruction before the previous one is done executing, ideally increasing speed sixfold

Pipelining (cont.) Must be aware of hazards: read-after-write, delayed branch Past 3-5 stage pipelines, the hazards become increasingly worse and more complex to deal with Works most efficiently when all instructions go through similar steps; not as efficient with more complex instruction sets.

Before The RISC Before 1980, complexity increased to lower semantic gap Frequently used operations implemented as microcode instead of instructions, causing bloat on the chip RISC was created to combat this, allowing more room for performance enhancing features

Reduced Instruction Set Computer (RISC) Modern version dated 1980's Some designs from the 60's and 70's could be viewed as a predecessor RISC I created by postgraduate class at Berkeley

RISC I Organization/Architecture Fixed instruction size (32-bit) CISC had variable length instruction sets Load-store architecture Instructions that process data only operated on registers, separate from those that accessed memory Thirty-two 32-bit registers All of them were general purpose registers

RISC Advantages Smaller die size – Simpler processor leaves more area for performance-enhancing features(ie. Cache memory, floating point hardware, etc.) Shorter development time – Simpler processor means less design effort and cost Higher performance – Smaller processor allows for higher clock rate(CISC often had higher but took longer)

RISC Drawbacks Generally had poor code density – Fixed-length instruction set consequence that required more main memory bandwidth without a cache and a higher cache miss rate with one, both resulting in higher power consumption Don't execute x86 code – Emulators can be used to bypass this issue, for the most part

Designing for Low Power Why low power?

CMOS Power Components Switching power Short-circuit power Leakage current

CMOS Circuit Power

Low Power Circuit Design

Lower Power Strategies Minimize Vdd Minimize off-chip activity Minimize on-chip activity Exploit parallelism

Sources ARM System-on-Chip Architecture, 2 nd Edition, Addison Wesley