Sequential logic circuits

Flip-Flops Has two or more inputs and one or two outputs, Q and Q’ Q’ always takes the opposite value of Q Outputs stay in a ‘0’ or ‘1’ state until new input values are applied (i.e. memory characteristic) The output may ‘flip’ to a ‘1’ or ‘flop’ to a ‘0’ or stay at the original state

Two Types of triggering for synchronous flip-flops Level Trigger -triggered by a whole positive or negative pulse Logic Symbols Edge Trigger -triggered by a positive edge (0-to-1 transition) or negative edge (1-to-0 transition) -better timing

Synchronous R-S flip-flop Types of flip-flops R-S flip-flop Synchronous R-S flip-flop J-K flip-flop D-type flip-flop T flip-flop

R-S Flip-flop -simplest type of flip-flop -operates in three modes (i.e. hold, reset, and set) Logic Symbol Truth Table

Logic Circuit Waveform Diagram

Synchronous R-S Flip-flop -similar to the normal R-S flip-flop except clock input -outputs change states only with clock pulse Logic Symbol Truth Table

Logic Circuit Waveform Diagram

J-K Flip-flop -always synchronous -operates in four modes (i.e. Hold, Set, Reset, and, Toggle) -Toggle Mode (i.e. change from 0-to1 or 1-to-0) is a very useful feature Logic Symbol Logic Circuit J K Truth Table

D-type Flip-flop -has one data input and a clock input -also called Delay Flip-flop because data at input D is delayed by one clock pulse before reaching output Q -next state of the output Q+ always follows data input D. Logic Symbol Truth Table Circuit

Dual D flip-flop (7474 TTL IC) Truth Table Logic Symbol Waveform Diagram

T flip-flop A T flip-flop can also be built using a JK flip-flop (J & K pins are connected together and act as T)

COUNTERS

Types of Counters i. Ripple Counters ii. Synchronous Counters -clock pulses are applied to the first flip-flop and signals ripple through the subsequent flip-flops -also called asynchronous counters Synchronous Counters -clock pulses are applied to all flip-flops -all flip-flop are triggered together in step with the clock pulse -can operate at much higher frequency than ripple counters more complex circuitry

4-bit Ripple Counter 4 bit counting -has 16 different levels (i.e. 0 0 0 0 to 1 1 1 1) -also called MOD-16 Counter -all flip-flops operate in Toggle Mode 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 4 bit counting

Truth Table

Waveforms Diagram Continue count until 1111 and then will automatically return to 0000 for recounting

Circuit Diagram

Decade Ripple Counter -has 10 different levels (i.e. 0 0 0 0 to 1 0 0 1) -also called MOD-10 Counter -all flip-flops operate in Toggle Mode -modification of MOD-16 Counter

Truth Table

Waveforms Diagram Recount until 1001 all over again

Circuit Diagram

4-bit Ripple Down Counter -Counting from the highest to the lowest number (i.e. 15, 14, 13,…..,0,) -All flip-flops operate in toggle mode.

Truth Table

Waveforms Diagram

Circuit Diagram

4-Bit Ripple Down Counter with self-stopping feature -all the counters discussed so far re-circulate (i.e. 0, 1, 2, ……, 15, 0, 1,2,……) -this counter stops at [0110] and does not re-circulate -all flip-flops except flip-flop A (LSB) operate in Toggle Mode -flip-flop A operates in Hold Mode when the OR Gate’s output is ‘0’ (i.e. QA = 0, QB = 1, QC = 1, and QD = 0)

Truth Table

Circuit Diagram

Synchronous Counters -clock pulses are applied to all flip-flops -all flip-flop are triggered together in step with the clock pulse -can operate at much higher frequency than ripple counters more complex circuitry 3-bit Synchronous Counter

4-bit Synchronous Counter

J-K flip-flops as Frequency Divider A frequency divider can be constructed from J-K flip-flops by taking the output of one cell to the clock input of the next. The J and K inputs of each flip-flop are set to 1 to produce a toggle at each cycle of the clock input. For each two toggles of the first cell, a toggle is produced in the second cell, so its output is at half the frequency of the first. The output of the fourth cell is 1/16 the clock frequency. The same device is useful as a binary counter. http://hyperphysics.phy-astr.gsu.edu/hbase/electronic/bincount.html#c1

SHIFT REGISTERS

What is a Shift Register ? -A group of flip-flops connected together to store binary numbers and to shift them from one flip-flop to another with every clock pulse -Commonly used as temporary storage between processing circuit and input and output -Can be also used for other purposes (e.g. ring counter, digital clock, modem, etc.)

Types of Shift Registers Serial-in / Serial-out (SISO) Serial-in / Parallel-out (SIPO) Parallel-in / Serial-out (PISO) Parallel-in / Parallel-out (PIPO)

3-bit SISO Shift Register Circuit Diagram Q0 Q1 Q2 Sequence Table -Output Q2 receives the data from input only after 3 clock pulses delay time. -Both input and output data are in serial format (i.e. one bit at one clock pulse)

3-bit SIPO Shift Register Circuit Diagram Sequence Table -Same circuit as SISO Shift Register except different output connection -The data is latched to output 3.bit at a time

3-bit PISO Shift Register Circuit Diagram Sequence Table -Clear input must be activated to clear all outputs of D flip-flops to ‘0’, before parallel data is loaded into -Parallel data must be loaded only once and reset to ‘0’. -Once the parallel data is loaded into the register, it will be shifted to right with every clock -Pulse data can be retrieved from ‘Data Out’ one bit at a time

3-bit PIPO Shift Register -Same circuit as PISO Shift Register except different output connection -Data is retrieved from the output (Q0, Q1, Q2) 3-bit at a time