Digital CFEB (an Update) B. Bylsma, EMU at CMS Week, March 16, Ben Bylsma The Ohio State University

SLHC Phase 1 Upgrade 2 B. Bylsma, EMU at CMS Week, March 16, 2009 Fully Instrument ME4/2 Chambers August 2009 Install/Instrument ME4/2 Test Chambers

OSU Digital CFEB 3 B. Bylsma, EMU at CMS Week, March 16, 2009 Replace SCA with Flash ADCs/Memories Better rate capability Similar Cost Propose 514 new cards ME1/1a Old cards to populate ME4/2 Upgrade Handle highest particle flux Restore ME1/1a triggering and readou t to  range

Current CFEB 4 B. Bylsma, EMU at CMS Week, March 16, 2009 pre SCA ADC + - ref 16 FPGA 12 bits muxmux 21 bits Chan- link 21:3 To DMB over Skewclear 280 Mbps eventLCTRelease Caps ~20µS L1A ~3.2µS Analog storage with L1A*LCT coincidence Analog storage - no coincidence Analog storage Digitization and Readout Basic Block Diagram: Time Line: Analog samples are stored until L1A. Then ADC must digitize 8X16 samples one at a time. Limited number of capacitors and single channel ADC impose constraints on LCT and L1A latencies. 6 layers 8 Triad signals pre comp layers 24 bits LVDS To TMB over Skewclear 80 MHz 2:1 3x8

New Digital CFEB 5 B. Bylsma, EMU at CMS Week, March 16, 2009 Basic Block Diagram: Time Line: No Dead Time. All 96 channels continuously digitized (no multiplexing). eventLCT~20µSL1A ~3.2µS FIFO Readout Pipeline Digitization Latency xfer pre ADC + - ref 16 FPGA 8 pairs layers Serial Opt. Trnscvr To DMB over Fiber ~1Gbps MGT ADC ref 8 pairs 16 pairs Pipeline/FIFOs Serial LVDS 8 Triad signals pre comp layers 48 To TMB over Skewclear Serial Opt. Trnscvr ~2Gbps MGT

First Step – Choose ADC 6 B. Bylsma, EMU at CMS Week, March 16, 2009 ADC choice drives subsequent design considerations  Interface between pre-amp and ADC  Voltage/Power requirements -Could impact LVDB design ADC choices: (8 ch, 12 bit, MSPS, Serial LVDS output)  MAX1437 (Maxim) 1.8V supply, 1.4V pp range  ADC12EU050 (National) 1.2V supply, 2.1V pp range  AD9222 (Analog Devices) 1.8V supply, 2V pp range  ADS5281 (Texas Instr.) 3.3V analog, 1.8V digital, 2V pp range

Issues with ADCs 7 B. Bylsma, EMU at CMS Week, March 16, 2009 None are suitable drop-in replacements for SCA/ADC -ADC’s  All have differential inputs  Limits on common mode  Have internal input bias network -Pre-Amp  Single ended output  Limited range of baseline level  Designed to drive small capacitive load -Pre-Amp/ADC Interface  Mnfr. suggest transformer coupling (not an option for us)  Amplifier to generate differential signal (requires 96 amplifiers)  Direct couple single ended signal (common mode consequences) (level shifting/scaling)  AC couple single ended signal (common mode consequences) (no level shifting, but still have biasing to consider)

Evaluation Boards 8 B. Bylsma, EMU at CMS Week, March 16, 2009 Purchased Evaluation Boards for ADS5281 and AD9222 Basic Setup: Input Circuitry ADC + - DeSer Logic Analyzer Identify constraints/operation limits of ADC  Direct Coupling Concerns -Common Mode  Data Sheet: V cm = 1.5  V  How far from nominal?  Baseline Level -Range  Digital output range is 2V  But is linear range of common mode 2V?  AC Coupling Concerns -Same as direct coupling -No worries with pre-amp baseline level -But need to bias positive input

Constraints (ADS5281) 9 B. Bylsma, EMU at CMS Week, March 16, 2009 ADC Constraints:  V cm -600mV < (IN+ + IN-)/2 < V cm +300mV (1.8V pp on IN+)  (IN- -1V) < IN+ < (IN-+1V) (ADC output range) Pre-Amp Constraints:  Baseline Level -Currently 1.8V -Max ~2.0V -Min ~1.2V (maybe 1.0V)  Drive Capability -Small (few mA at best) Scaling:  Scale down input  Add digital gain on output  Resistor divider V cm 1.2k

Digitize Amplifier Pulses 10 B. Bylsma, EMU at CMS Week, March 16, 2009 Connect CFEB to Evaluation Board: 50ns samples

Current DCFEB R&D Status 11 B. Bylsma, EMU at CMS Week, March 16, 2009 Evaluating ADC Exploring Options for Interfacing to ADC  Direct Coupling  AC Coupling  Amplifier Coupling  Scaling