Unrolling Carry Recurrence

Slides:

Advertisements

Similar presentations

L23 – Adder Architectures. Adders  Carry Lookahead adder  Carry select adder (staged)  Carry Multiplexed Adder  Ref: text Unit 15 9/2/2012 – ECE 3561.

Advertisements

Carry Lookahead Homework

Introduction So far, we have studied the basic skills of designing combinational and sequential logic using schematic and Verilog-HDL Now, we are going.

CPE 626 CPU Resources: Adders & Multipliers Aleksandar Milenkovic Web:

Using Carry-Save Adders For Radix- 4, Can Be Used to Generate 3a – No Booth’s Slight Delay Penalty from CSA – 3 Gates.

Fast Adders See: P&H Chapter 3.1-3, C Goals: serial to parallel conversion time vs. space tradeoffs design choices.

UNIVERSITY OF MASSACHUSETTS Dept

CSE-221 Digital Logic Design (DLD)

1 CS 140 Lecture 14 Standard Combinational Modules Professor CK Cheng CSE Dept. UC San Diego Some slides from Harris and Harris.

1 A Timing-Driven Synthesis Approach of a Fast Four-Stage Hybrid Adder in Sum-of-Products Sabyasachi Das University of Colorado, Boulder Sunil P. Khatri.

Space vs. Speed: Binary Adders 11.3 Space vs. Speed.

EECS Components and Design Techniques for Digital Systems Lec 18 – Arithmetic II (Multiplication) David Culler Electrical Engineering and Computer.

1 Design of a Parallel-Prefix Adder Architecture with Efficient Timing-Area Tradeoff Characteristic Sabyasachi Das University of Colorado, Boulder Sunil.

ECE C03 Lecture 61 Lecture 6 Arithmetic Logic Circuits Hai Zhou ECE 303 Advanced Digital Design Spring 2002.

Introduction to CMOS VLSI Design Lecture 11: Adders

CSC 110 – Intro to Computing Lecture 14: Midterm Review.

Digital Design – Optimizations and Tradeoffs

Modern VLSI Design 2e: Chapter 6 Copyright  1998 Prentice Hall PTR Topics n Shifters. n Adders and ALUs.

Lecture 8 Arithmetic Logic Circuits

Fall 2008EE VLSI Design I - © Kia Bazargan 1 EE 5323 – VLSI Design I Kia Bazargan University of Minnesota Adders.

Lecture 17: Adders.

Lecture 12b: Adders. CMOS VLSI DesignCMOS VLSI Design 4th Ed. 17: Adders 2 Generate / Propagate  Equations often factored into G and P  Generate and.

Spring 2002EECS150 - Lec10-cl1 Page 1 EECS150 - Digital Design Lecture 10 - Combinational Logic Circuits Part 1 Feburary 26, 2002 John Wawrzynek.

Chapter 5 Arithmetic Logic Functions. Page 2 This Chapter..  We will be looking at multi-valued arithmetic and logic functions  Bitwise AND, OR, EXOR,

VLSI Digital System Design 1.Carry-Save, 2.Pass-Gate, 3.Carry-Lookahead, and 4.Manchester Adders.

Adders. Full-Adder The Binary Adder Express Sum and Carry as a function of P, G, D Define 3 new variable which ONLY depend on A, B Generate (G) = AB.

Parallel Prefix Adders A Case Study

Introduction to CMOS VLSI Design Lecture 11: Adders David Harris Harvey Mudd College Spring 2004.

Bar Ilan University, Engineering Faculty

1. Copyright  2005 by Oxford University Press, Inc. Computer Architecture Parhami2 Figure 10.1 Truth table and schematic diagram for a binary half-adder.

Abdullah Aldahami ( ) Feb26, Introduction 2. Feedback Switch Logic 3. Arithmetic Logic Unit Architecture a.Ripple-Carry Adder b.Kogge-Stone.

1 Design Space Exploration for Power-Efficient Mixed-Radix Ling Adders Chung-Kuan Cheng Computer Science and Engineering Depart. University of California,

WEEK #10 FUNCTIONS OF COMBINATIONAL LOGIC (ADDERS)

Chapter # 5: Arithmetic Circuits

Chapter 6-1 ALU, Adder and Subtractor

Digital Logic Computer Organization 1 © McQuain Logic Design Goal:to become literate in most common concepts and terminology of digital.

1 CPSC3850 Adders and Simple ALUs Simple Adders Figures 10.1/10.2 Binary half-adder (HA) and full-adder (FA). Digit-set interpretation: {0, 1}

Design of a 32-Bit Hybrid Prefix-Carry Look-Ahead Adder

Nov 10, 2008ECE 561 Lecture 151 Adders. Nov 10, 2008ECE 561 Lecture 152 Adders Basic Ripple Adders Faster Adders Sequential Adders.

July 2005Computer Architecture, The Arithmetic/Logic UnitSlide 1 Part III The Arithmetic/Logic Unit.

Modern VLSI Design 4e: Chapter 6 Copyright  2008 Wayne Wolf Topics n Shifters. n Adders and ALUs.

درس مدارهای منطقی دانشگاه قم مدارهای منطقی محاسباتی تهیه شده توسط حسین امیرخانی مبتنی بر اسلایدهای درس مدارهای منطقی دانشگاه.

CHAPTER 4 Combinational Logic Design- Arithmetic Operation (Section 4.6&4.9)

Fast Adders: Parallel Prefix Network Adders, Conditional-Sum Adders, & Carry-Skip Adders ECE 645: Lecture 5.

Spring C:160/55:132 Page 1 Lecture 19 - Computer Arithmetic March 30, 2004 Sukumar Ghosh.

Binary Adder DesignSpring Binary Adders. Binary Adder DesignSpring n-bit Addition –Ripple Carry Adder –Conditional Sum Adder –(Carry Lookahead.

COMP541 Arithmetic Circuits

CS221: Digital Logic Design Combinational Circuits

Block p and g Generators. Carry Determination as Prefix Computations Two Contiguous (or Overlapping) Blocks (g’, p’) and (g’’, p’’) Merged Block (g, p)

COMP541 Arithmetic Circuits

Conditional-Sum Adders Parallel Prefix Network Adders

Digital Design Module –II Adders Amit Kumar Assistant Professor SCSE, Galgotias University, Greater Noida.

Computer Architecture Lecture 16 Fasih ur Rehman.

EE466: VLSI Design Lecture 13: Adders

Digital Integrated Circuits 2e: Chapter Copyright  2002 Prentice Hall PTR, Adapted by Yunsi Fei ECE 300 Advanced VLSI Design Fall 2006 Lecture.

1 Carry Lookahead Logic Carry Generate Gi = Ai Bi must generate carry when A = B = 1 Carry Propagate Pi = Ai xor Bi carry in will equal carry out here.

CPEN Digital System Design

Addition, Subtraction, Logic Operations and ALU Design

Full Tree Multipliers All k PPs Produced Simultaneously Input to k-input Multioperand Tree Multiples of a (Binary, High-Radix or Recoded) Formed at Top.

CSE 311 Foundations of Computing I Lecture 25 Circuits for FSMs, Carry-Look-Ahead Adders Autumn 2011 CSE 3111.

1. 2 Figure 10.1 Truth table and schematic diagram for a binary half-adder Simple Adders Half-adder.

Carry-Lookahead, Carry-Select, & Hybrid Adders ECE 645: Lecture 2.

Topic: N-Bit parallel and Serial adder

EE141 Arithmetic Circuits 1 Chapter 14 Arithmetic Circuits Rev /12/2003.

Full Adder Truth Table Conjugate Symmetry A B C CARRY SUM

Conditional-Sum Adders Parallel Prefix Network Adders

Divide-and-Conquer Design

CSE Winter 2001 – Arithmetic Unit - 1

Conditional-Sum Adders Parallel Prefix Network Adders

Presentation transcript:

Unrolling Carry Recurrence

Carry-Lookahead Equations

4-Bit CLA

Circuit Structure

CLA Complexity

Managing CLA Complexity

Multilevel CLA Example

Radix-16 Addition Two Binary Numbers Grouped into Hex Digits Block Generate and Propagate Signals in Each radix-16 Digit Replace c4 Position of CLA Network with Block Signals g[i,i+3] and p[i,i+3] Results in 4-bit “Lookahead Carry Generator”

CLA Design

Lookahead Carry Generator

Block Generate and Propagate Assume i0 < i1 < i2 Example: g[0,3] is Generate Signal of Block for bits 0-3 Relationships Allow for Merging of Blocks Can Allow Merged Block to Overlap

Lookahead Carry Generator Example Merged LAG x15-12 y15-12 x11-8 y11-8 x7-4 y7-4 x3-0 y3-0 CLA 3 c12 CLA 2 c8 CLA 1 c4 CLA c0 g15-12 p15-12 g11-8 p11-8 g7-4 p7-4 g3-0 p3-0 s15-12 s11-8 s7-4 s3-0 Lookahead Carry Generator g15-0 p15-0

CLA Latency

CLA Architecture

Overlapped LAGs Overlap Blocks [i1,j1] and [i0,j0] Relationships Become: Useful for Building Trees of Different Shapes

CLA With LAG

CLA Latency Example: 64-bit CLA in 13 gate levels since 43 = 64 Generates final carry out for Fig. 6.5

Ling Adders

Ling Adders – Wired OR

Block p and g Generators

Carry Determination as Prefix Computations Two Contiguous (or Overlapping) Blocks (g, p) and (g, p) Merged Block (g, p) g = g + gp  p = p p Large Group Generates Carry if: left group generates carry right group generates and left group propagates

Carry Operator, ¢ Define Operator Over (g, p) Pairs (g, p) = (g, p ) ¢ (g, p) g = g + g p p = p p ¢ is Associative (g, p) ¢ (g, p) ¢ (g, p) = [(g, p) ¢ (g, p) ] ¢ (g, p) = (g, p) ¢ [(g, p) ¢ (g, p)]

Carry Operator, ¢ (cont) ¢ is NOT Commutative (g, p) ¢ (g, p)  (g, p)¢ (g, p) This is Easy to See Because: g = g+ gp  g+ g p

Prefix Adders

Carry Determination Assume Adder with NO cIN ci+1 = g[0,i] Carry Enters i+1 Block iff Generated in Block [0,i] Assume Adder with cIN = 1 Viewed as Generated Carry from Stage -1 p-1 = 0, g-1 = cIN Compute g[-1,i] For All i Formulate Carry Determination as:

Prefix Computation

Prefix Sums Analogy Designs for Prefix Sums Can be Converted to Carry Computation Replace Adder with ¢ Operator Addition IS Commutative, Order Doesn’t Matter Can Group (g, p) In Anyway to Combine Into Block Signals (as long as order is preserved) (g, p) Allow for Overlapping Groups, Prefix Sums Does Not (sum would contain some values added two or times)

Prefix Sum Network (adder levels) (# of adders)

Another Way for Prefix Sums Compute the Following First: x0+x1 x2+x3 x4+x5 ... xk-2+xk-1 Yields the Partial Sums, s1, s3, s5, ..., sk-1 Next, Even Indexed Sums Computed As: s2j = s2j-1 + x2j

Alternative Prefix Sum Network

Comparison of Prefix Sum Networks First Design Faster: lg2(k) versus 2lg2(k)-2 (levels) First Design has High Fan-out Requirements First Design Requires More Cells (k/2)lg2k versus 2k-2-lg2k Second Design is Brent-Kung Parallel Prefix Graph First Design is Kogge-Stone Parallel Prefix Graph (fan-out can be avoided by distributing computations)

Brent-Kung Network independent, so single delay

Kogge-Stone Network

Area/Levels of Prefix Networks

Hybrid Parallel Prefix Network