CS 211: Computer Architecture Lecture 2 Instructor: Morris Lancaster

Appendix B Instruction Set Principles and Examples

5/7/2010CS 211 Lecture 23 ?Design a New High Performance System? ISA –What instructions should we include Internal Organization –How do the instructions implemented affect the internal organization (and subsequently performance) How best approach this problem? –Understand what a computer and an instruction set architecture does for us –Look at current architectures for insight

5/7/2010CS 211 Lecture 24 Classifying ISA’s Type of Internal Storage –Stack –Accumulator –Set of Registers

5/7/2010CS 211 Lecture 25 Operand Locations for 4 ISA Classes

5/7/2010CS 211 Lecture 26 Design Decisions Instruction Set Architecture Class (Load-Store?) –How Many Registers (more is good) How Many Operands in the instruction?

5/7/2010CS 211 Lecture 27 Code Sequences for the 4 Classes Since 1980s almost all new designs are load store architectures. –Machines have large register files –Registers are easier for the compiler to manage (addressed in only one way) StackAccumulatorRegister (register-memory) Register (load store) Push ALoad ALoad R1, A Push BAdd BAdd R3, R1, BLoad R2, B AddStore CStore R3, CAdd R3, R1, R2 Pop CStore R3,C

5/7/2010CS 211 Lecture 28 Number of Memory Addresses Number of memory addresses Maximum number of operands allowed Type of Architecture Examples 03Load-StoreAlpha, ARM, MIPS, PowerPC, SPARC, SuperH, TM32 12Register-MemoryIBM 360/370, Intel 80x86, Motorola 68000, TI TMS320C54x 22Memory – memoryVAX (also has 3 operand formats) 33Memory - memoryVAX (also has 2 operand formats)

5/7/2010CS 211 Lecture 29 Tradeoffs for the ISA Classes TypeAdvantagesDisadvantages Register-register (0,3) Simple, fixed length instruction encoding. Simple code generation model. Instructions take similar numbers of clocks to execute. Higher instruction count than architectures with memory references in the instructions. More instructions and lower instruction density leads to larger programs Register-memory (1,2) Data can be accessed without a separate load instruction first. Instruction format tends to be easy to encode and yields good density Operands are not equivalent since a source operand is destroyed. Encoding a register number and a memory address in each instruction may restrict the number of registers. Clocks per instruction vary by operand location Memory-memory (2,2) or (3,3) Most compact. Does not waste registers for temporaries. Large variation in instruction size, especially for three-operand instructions. In addition, large variation in work per instruction. Memory accesses create memory bottleneck. (Not used today)

5/7/2010CS 211 Lecture 210 Memory Addressing (page B9) RegisterAdd R4,R3R4<- R4 + R3 ImmediateAdd R4,#3R4<- R4 + 3 Displacement Add R4,100(R1) R4<- R4 + Mem[100+R1] Register IndirectAdd R4,(R1) R4<- R4 + Mem[R1] IndexedAdd R3,(R1+R2) R3<- R3 + Mem[R1+R2] DirectAdd R1, (1001) R1<- R1 + Mem[1001] Memory IndirectAdd R1<- R1 + Mem[Mem[R3]] AutoIncrementAdd R1, (R2)+R1<- R1 + Mem[R2] R2<- R2 +d AutoDecrementAdd R1, -(R2) R2<- R2 - d R1<- R1 + Mem[R2] ScaledAdd R1, 100(R2)[R3]R1<- (R1) + Mem[100+(R2) + (R3)*d]

5/7/2010CS 211 Lecture 211 Summary of Use of Addressing Modes for DEC VAX Architecture

5/7/2010CS 211 Lecture 212 Displacement Values Are Widely Distributed

5/7/2010CS 211 Lecture 213 About ¼ of Data Transfers and ALU Operations Have an Immediate Operand

5/7/2010CS 211 Lecture 214 Distribution of Immediate Values

5/7/2010CS 211 Lecture 215 Type and Size of Operands 8, 16, 32, 64 bits Alignment Fetch capability Encoding type

5/7/2010CS 211 Lecture 216 Distribution of Data Access By Size

5/7/2010CS 211 Lecture 217 Control Flow Addressing modes Conditional branch operations Frequency distributions

5/7/2010CS 211 Lecture 218 Breakdown of Control Flow Instructions

5/7/2010CS 211 Lecture 219 Branch Distance In Number of Instructions

5/7/2010CS 211 Lecture 220 Frequency of Different Types of Compares in Conditional Branches

5/7/2010CS 211 Lecture 221 Fig 2.38 Data Reference Sizes

5/7/2010CS 211 Lecture 222 Fig 2.23 Three Variations In Instruction Encoding

5/7/2010CS 211 Lecture 223 Instruction Encoding Balance –Desire to have as many registers and addressing modes as possible –The impact of the size of the register and addressing mode fields on the average instruction size and hence average program size –A desire to have instructions encoded into lengths that will be easy to handle in a pipelined implementation

5/7/2010CS 211 Lecture 224 The Role of Compilers Structure Optimizations Register Allocation (tied with hardware) Impact of Compiler Technology on Architects Decisions

5/7/2010CS 211 Lecture 225 Fig 2.24 Compiler Structure

5/7/2010CS 211 Lecture 226 Fig 2.26 Change in Instruction Count From Compiler Optimization (SPEC2000)

5/7/2010CS 211 Lecture 227 MIPS Instruction Set MIPS 64 has 32 general purpose registers of 64 bits in length (R0…R31) –Value of R0 is always 0 32 floating point registers capable of holding 32 or 64 bit floating point numbers Instruction formats –I type immediate –R type register-register –J type jump

5/7/2010CS 211 Lecture 228 MIPS Instruction Set Instruction nomenclature –Opcode –Registers rs, rd, rt

5/7/2010CS 211 Lecture 229 Fig 2.27 MIPS Instruction Layout

5/7/2010CS 211 Lecture 230 Fallacies and Pitfalls Pitfall – Designing a “high-level” instruction set feature specifically oriented to supporting a high-level language structure. Fallacy – There is such a thing as a typical program Pitfall – Innovating at the instruction set architecture to reduce code size without accounting for the compiler. Fallacy – An architecture with flaws cannot be successful Fallacy – You can design a flawless machine