Different Microprocessors Tamanna Haque Nipa Lecturer Dept. of Computer Science Stamford University Bangladesh

Difference between 8086 &8088 External Data Path: 8 bit for 8088 and 16 bit for 8086 Memory Access: 8088 access memory in byte while 8086 can access memory both bytes and words has faster clock rate and better performance then is less expensive than 8086.

80186/80188 Enhanced version of 8086/8088 The 6/8 MHz clock provides 2 times greater throughput than the 5MHz 8086/ pin package On chip priority interrupt controller chip to provide 5 interrupt pins 1 megabyte of memory can be addressed Instructions set as 8086 and 10 new instructions (extended instruction set)

8086/8088 General Registers ALU Control Instruction Decoder Segment Register Bus Interface Prefetcher Prefetch queue 16 bit data or operand request Prefetch Instruction 20 bit address bus multiplexed with data bus

8086/ units:  Execution unit  Bus interface unit Both units are independent and operates parallel to each other to maximized th performance.

Execution unit It executes all instructions as well as manipulating the general registers and the status and control flags. It sends data and address to the BIU when required Instructions are fed to EU over 8 bit wide prefetch queue bus Instructions are processed by the control system ALU, registers and internal data path are 16 bits wide

Bus Interface Unit The BIU processes all requestes from the EU to read data from or write data to memory or I/O device All requests pass through to BIU and it combines the segment and offsets to form the physical address using a dedicated hardware adder Prefetch queue is a small FIFO RAM array, used to prefetch instruction following the current executing instruction for EU when the BIU is free

Bus Interface Unit Prefetch queue in 8088 hold 4 bytes and BIU begins a fetch cycle whenever one or more bytes empty in the queue. Prefetch queue in 8086 hold 6 bytes and BIU begins a fetch cycle whenever one or more bytes empty in the queue. When an instruction causes program control to be transferred to the non-sequential location then the prefetch instruction no longer be valid. Then BIU flushes the prefetch queue and immediately starts an instruction fetch at the target address.

Features of bit address bus. 16 bit data bus Able to address 16 MB of physical memory. It has a MMU[memory management unit] 68 pins 6 times faster than 8086 Used for multiuser and multitasking

80286 It operates in 2 modes  Real address mode: behaves like 8086 and program for 8086 can run directly.  Protected virtual address mode: it supports maltitasking, so several program runs at the same time and memory protection is required to protect the memory used by one program from the action of other program  Can address 16 megabye of physical address in protected mode and 1 GB of virtual memory.

Features of cont… Register organization of  Eight 16-bit general purpose registers  Four 16-bit segment registers  Status & control registers  Instruction pointer

80286 Instruction Decoder Decoded Instruction Queue General Registers ALU Control Physical Address Generator Segment Registers Segment Descriptor Cache Bus Interface Prefetcher Prefetch Queue 16 bit offsets and data Operand request Decoded instruction Execution Unit Instruction Unit Physical address (24 bits) Address unit BIU Address bus 24 bits Data bus 16 bits

Processing Unit 4 Processing Unit  Address unit  Bus unit  Instruction unit  Execution unit All units are independent and operates asynchronously and in parallel with the others.

Execution unit Execution unit manipulates the general register as well as the status and control flags and executes all instructions. The ALU performs the arithmetic and logical operations that are required by the instruction. ALU also maintain the CPU status and control flags. General registers are used to moves data to or from the registers as required.

BUS Interface Unit It handles all communications and data transfer between CPU and the system bus. It generates the address, commands and data signals required to access memory and I/O devices. Data and address bus are not multiplexed. The BIU uses the idle bus cycles to pre- fetch instructions

BUS Interface Unit cont… Pre-fetch queue is 6 bytes long and whenever 2 or more bytes of pre-fetch queue becomes empty the pre-fetch cycle occurs. A control transfer instruction causes the BIU flush the queue and immediately begin loading the instruction from the new address.

The Instruction Unit It decodes the pre-fetched instruction bytes for execution unit. Up to 3 fully decoded instructions are available in the queue provided by the instruction unit.

The Address Unit In real mode the address unit works same as in the segment and offset values are summed together by a dedicated adder to produce a physical memory address. In protected mode, every memory references, including code pre-fetches, must be checked against the permissions and segment limits of the current task to detect memory protection violations. After the permission, the logical address needs to translate to a physical address for use by the BIU. A cache has been designed into the address unit named segment descriptor cache register.

The Address Unit One segment descriptor cache register is provided for each of the four segment register. When a segment register is loaded with a new value, the segment descriptor specifying access right, segment base address and address size associated with that value is automatically loaded into the appropriate segment descriptor cache register. segment descriptor cache register is only accessed by the address unit.

80386 Similar to but enhanced 6 parts:  BIU  Code Prefetch Unit  Instruction Decode unit  Execution Unit  Segmentation Unit  Paging Unit Six level of pipelining makes it more faster Each part can work independently and parallel to each other. So different part can process different instruction at a time.

80386 Translation Lookaside buffer Page translator Segment register Segment Descriptor Cache Segment translator Instruction decoder Decoded Instruction Queue Protection test unit General Registers Barrel shifter ALU Multiply/Divide Control Prefetcher Prefetch Queue BIU Operand request Decoded instruction Execution Unit Instruction Decode Unit Physical address Address bus Data bus Code prefetch unit Segmentation Unit Paging Unit Effective address 32 bits Linear address

Additional hardware The performance of has been also improved by some additional hardware  64 bit barrel shifter: a specialized hardware that performs multiple bit shifts in a single clock cycle.  3 input adder dedicated to effective address processing  An early-out multiplier : terminates the multiply algorithm when no significant digits remain to be processed.

386DX and 386SX Difference between 80386DX and 80386SX is the width of the external address and data buses. Internally both uses 32 bit pathways. The address bus of 386DX is 32 bits wide and can directly address 4 gigabytes (2 32 bytes) of physical memory The address bus of 386SX is 24 bits wide and can directly address 16 Mb (2 24 bytes) of physical memory

Bus Interface Unit All requests for access to the bus that comes from the other on chip processing unit passes through the BIU Because of the parallel operation of other parts of the microprocessor, it is possible that more than one bus request may be received by the BIU at the same time BIU also queue and prioritize these requests. To avoid the delaying program execution, request from EU have highest priority Every unit can independently communicate with BIU.

The Code Pre-fetch Unit Operates same as can store 16 bytes of prefetch instruction

The instruction decode unit 3 decoded instruction can be saved in decoded instruction queue Same as 80286

Execution Unit The function of the EU can be divided into 3 major parts: Control unit: the function of control unit is to speed up certain types of operations including multiplies, divides and effective address calculations. Data unit: it contains ALU and eight 32 bit general registers of the it includes 64 bit barrel shifter and an early out multiplier. The protection test unit: it monitors memory to detect segmentation violations.

Segmentation unit It performs the first stage of address translation, converting the logical address to linear address. Segment descriptor caches are employed both to speed up the translation and to allow protection violations to be detected without performance. The dedicated 3 input adder is also used to speed up

The Paging Unit It translate the linear address to physical address. If paging unit is not enable then physical address is the same as linear address. It contains a cache called translation lookaside buffer (TLB), which holds 32 most recently used page table entries.

80486 Microprocessor The 32-bit is the next evolutionary step up from the One of the most obvious feature included in a is a built in math coprocessor. This coprocessor is essentially the same as the processor used with a 80386, but being integrated on the chip allows it to execute math instructions about three times as fast as a 80386/387 combination is an 8Kbyte cache for both code and data is packaged in a 168 pin 25 to 66 MHz clock 32 bit data bus and 32 bit address bus

Translation Lookaside buffer Page translator Segment register Segment Descriptor Cache Segment translator Floating Point Control Floating Point Registers and Stack General Registers Barrel shifter ALU Multiply /Divide Prefetcher Prefetch Queue Integer Unit Prefetch unit Segmentation Unit Paging Unit Linear address Instruction decoder Control Protection test unit Cache controller 8k Cache Bus Interface Bus Size Control Burst Control Parity Generator and Control Write Buffers Instruction Decode unit Control unit Floating Point unit Cache unit 32 bit Address bus 32 bit Data bus Instruction word Micrpcode Entry Point 32 bit data Physical address

80486 Similar to but enhanced 9 parts:  BIU  Prefetch Unit  Instruction Decode unit  Control Unit  Floating Point Unit  Integer Unit  Segmentation Unit  Paging Unit  Cache Unit Six level of pipelining makes it more faster Each part can work independently and parallel to each other. So different part can process different instruction at a time bus provides support for parity checking, burst cycle, cacheable cycles and cache invalidation cycles, write buffering and can be configured dynamically for 8/16/32 bit data operations.

80486 The BIU exchange data internally only with cache and instruction prefetch unit. Requests from all other processing units pass through the cache unit first. All request for access to the bus are prioritized and executed by the BIU. The BIU reads data from the external bus 16 bytes at a time for transfer to cache unit. The BIU can buffer up to 32 bit write transfers to memory.

contains 8k of high speed of RAM configured an on chip cache and managed by the cache unit. An instruction prefetch cycle reads a 16 bytes block of memory. The prefetch queue can hold 32 bytes and accepts prefetches in 16 bytes transfer.

80486 The instruction decode unit reads prefetched instructions from the prefetch queue and translates the machine code bytes into control signals for the other processing unit. The control unit executes the instructions that have been decoded and control over the integer, floating point and segmentation unit The 2 32 bit data buses connecting the integer, cache and floating point unit are used together for transferring 64 bit operands in a single operation and has a separate 32 bit connection to the segmentation unit to pass the data to generate the effective address.

80486 The segmentation unit and the paging unit constitute the memory management unit in and are used to implement both memory protection and virtual memory management. Floating point unit is a integrated math coprocessor and execution speed is significantly improves when all operands are in registers or accessible in the cache. It is used to minimized the execution time.

Pentium Processor It is based on a superscalar design as the processor includes dual pipelining and executes more than one instruction per clock cycle is an 8Kbyte cache for code and 8Kbyte for data 60 to 100 MHz clock 64 bit data bus and 32 bit address bus It conation the complete instructions set with some new ones.

Pentium Processor The Pentium processor has 3 modes of operations: Real address mode: Pentium processor runs programs written for 8086/8088. Protected mode: Designed for memory management, protection, multitasking and multiprocessing. System management mode (SMM): It allows engineers to design for low power usage.

Pentium Processor It includes faster floating point on chip hardware than Faster algorithms provide up to ten times speed up for common operations such as add, multiply and load. The two instruction pipelines and on chip floating point unit are capable of independent operations. Each pipeline issues frequently used instructions in a single clock cycle. The dual pipelines an jointly issue 2 integer instruction in one clock cycle. Or one floating point instruction in one clock cycle.

Pentium Processor Branch prediction is implemented in the Pentium by using two prefetch buffer: one to prefetch code in a linear fashion and one to prefetch code according to the contains of the Branch Target Buffer (BTB) so the required code is almost always prefetched before it is needed for execution. It includes 8 Kbytes on chip code cache and 8 Kbytes of data cache. Each cache is two way set associative and each cache has a dedicated Translation Lookaside Buffer (TLB) to translate linear address to physical address used by each cache.

Pentium Processor There are 2 instruction pipelines, the ‘U’ pipe and the “V” pipe which are nor equivalent and interchangeable. The “U” pipe can execute all integer and floating point instructions. The “V” pipe can only execute simple integer instructions and floating point exchange register contents instructions. The instruction decode unit decodes the prefetched instructions so that the Pentium can execute them. The control ROM includes the micro code for the Pentium processor and has direct control over both pipelines. A barrel shifter is included in the chip for fast shift operations.