Joel Goldstein, RAL 4th ECFA/DESY LC Workshop, 1/4/2003 1 Vertex Readout Joel Goldstein PPd, RAL 4 th ECFA/DESY LC Workshop DAQ Session 1 st April 2003.

Slides:

Advertisements

Similar presentations

Konstantin Stefanov, Rutherford Appleton Laboratory4 th ECFA-DESY Workshop, 1-4 April 2003p. 1 CCD-based Vertex Detector - LCFI status report Konstantin.

Advertisements

The Status of the LCFI Project Snowmass 2005 Joel Goldstein CCLRC Rutherford Appleton Laboratory For the LCFI Collaboration.

Latest Developments from the CCD Front End LCWS 2005 Stanford Joel Goldstein, RAL for the LCFI Collaboration.

Konstantin Stefanov, Rutherford Appleton Laboratory UTA LC Workshop, 8 Jan Report from the LCFI collaboration Konstantin Stefanov RAL Introduction:

January US LC Workshop SLAC – Chris Damerell 1 Strategies for pickup and noise suppression with different vertex detector technologies Chris Damerell.

LCFI Collaboration Status Report LCWS 2004 Paris Joel Goldstein for the LCFI Collaboration Bristol, Lancaster, Liverpool, Oxford, RAL.

6 Mar 2002Readout electronics1 Back to the drawing board Paul Dauncey Imperial College Outline: Real system New VFE chip A simple system Some questions.

Victoria04 R. Frey1 Silicon/Tungsten ECal Status and Progress Ray Frey University of Oregon Victoria ALCPG Workshop July 29, 2004 Overview Current R&D.

20 Feb 2002Readout electronics1 Status of the readout design Paul Dauncey Imperial College Outline: Basic concept Features of proposal VFE interface issues.

Vertex 2002, Kona, Hawaii S.Xella – Rutherford Appleton Laboratory A vertex detector for the next linear collider Stefania Xella on behalf of the LCFI.

1 Instrumentation DepartmentMicroelectronics Design GroupR. Turchetta 3 April 2003 International ECFA/DESY Workshop Amsterdam, 1-4 April 2003 CMOS Monolithic.

Konstantin Stefanov, CCLRC Rutherford Appleton Laboratory PPRP open session: LCFI, IoP, 8 th September Linear Collider Flavour Identification (LCFI)

A new idea of the vertex detector for ILC Y. Sugimoto Nov

R&D Status of FPCCD Vertex Detector Dec.1, 2006 Yasuhiro Sugimoto KEK.

Development of Readout ASIC for FPCCD Vertex Detector 01 October 2009 Kennosuke.Itagaki Tohoku University.

Study of FPCCD Vertex Detector 12 Jul. th ACFA WS Y. Sugimoto KEK.

Nicolo de Groot, Rutherford Appleton LaboratoryDESY PRC, 7/8 May 2003p. 1 CCD-based Vertex Detector - LCFI status report Nicolo de Groot RAL/Bristol Conceptual.

Fine Pixel CCD Option for the ILC Vertex Detector

July US LC Workshop Cornell U – Chris Damerell 1 A CCD-based vertex detector Chris Damerell on behalf of the LCFI Collaboration Project overview.

ALCPG Workshop, Cornell, July '03 1 G. Eckerlin Data Acquisition for an LC Detector Report from the extended ECFA/DESY LC Workshops Cornell, Jul. 15 th.

Understanding Data Acquisition System for N- XYTER.

VC Feb 2010Slide 1 EMR Construction Status o General Design o Electronics o Cosmics test Jean-Sebastien Graulich, Geneva.

LCFI Collaboration Status Report LCUK Meeting Oxford, 29/1/2004 Joel Goldstein for the LCFI Collaboration Bristol, Lancaster, Liverpool, Oxford, QMUL,

SLAC LCD Meeting, Jan 27 th 2005G. Eckerlin, DESY 1 Data Acquisition for the ILC G. Eckerlin DESY LCD Group meeting, SLAC, Jan 27 th 2005 Outline Conditions.

Pixel hybrid status & issues Outline Pixel hybrid overview ALICE1 readout chip Readout options at PHENIX Other issues Plans and activities K. Tanida (RIKEN)

Frontend of PHENIX Si pixel K. Tanida (RIKEN) FEM/DAQ meeting for PHENIX upgrade (10/24/02) Outline Overview of PHENIX Si pixel detector ALICE1 chip readout.

Leo Greiner IPHC DAQ Readout for the PIXEL detector for the Heavy Flavor Tracker upgrade at STAR.

Development of an ASIC for reading out CCDS at the vertex detector of the International Linear Collider Presenter: Peter Murray ASIC Design Group Science.

Vertex Detector for GLD 3 Mar Y. Sugimoto KEK.

Impact parameter resolution study for ILC detector Tomoaki Fujikawa (Tohoku university) ACFA Workshop in Taipei Nov

1 Engineering issues for FPCCD VTX Detector Y. Sugimoto KEK July 24, 2007.

Super-Belle Vertexing Talk at Super B Factory Workshop Jan T. Tsuboyama (KEK) Super B factory Vertex group Please visit

Leo Greiner PIXEL Hardware meeting HFT PIXEL detector LVDS Data Path Testing.

Fine Pixel CCD for ILC Vertex Detector ‘08 7/31 Y. Takubo (Tohoku U.) for ILC-FPCCD vertex group ILC vertex detector Fine Pixel CCD (FPCCD) Test-sample.

DAQ for 4-th DC S.Popescu. Introduction We have to define DAQ chapter of the DOD for the following detectors –Vertex detector –TPC –Calorimeter –Muon.

FPCCD Vertex detector 22 Dec Y. Sugimoto KEK.

BTeV Hybrid Pixels David Christian Fermilab July 10, 2006.

Prague, Marcel Trimpl, Bonn University DEPFET-Readout Concept for TESLA based on Current Mode Signal Processing Markus Schumacher on behalf.

1 FPCCD VTX Work Plan Y. Sugimoto 2010/1/22. 2 FPCCD: Features and R&D issues (1/2) Small pixel size (~5  m) –Sensor development Small size chip; ~6mm.

Andrei Nomerotski, University of Oxford ILC VD Workshop, Menaggio 22 April 2008 SiD Vertex Detector.

FPCCD VTX Work Plan Y. Sugimoto 2010/1/22. FPCCD: Features and R&D issues (1/2) Small pixel size (~5  m) –Sensor development Small size; ~6mm x 6mm Full.

1 Konstantin Stefanov, Rutherford Appleton Laboratory 1 LCWS2007 Progress with the CPCCD and the ISIS Konstantin Stefanov Rutherford Appleton Laboratory.

ECFA Workshop, Warsaw, June G. Eckerlin Data Acquisition for the ILD G. Eckerlin ILD Meeting ILC ECFA Workshop, Warsaw, June 11 th 2008 DAQ Concept.

5 May 2006Paul Dauncey1 The ILC, CALICE and the ECAL Paul Dauncey Imperial College London.

Vertex detector R&D Work Plan in /3/11 Y. Sugimoto for KEK-Tohoku-TohokuGakuin-Niigata- ToyamaCMT Collaboration.

Sonja Hillert, University of Oxford2 nd ECFA LC workshop, Durham, 1 st September 2004 p. 0 Recent results from R&D towards a vertex detector at the international.

FPGA based signal processing for the LHCb Vertex detector and Silicon Tracker Guido Haefeli EPFL, Lausanne Vertex 2005 November 7-11, 2005 Chuzenji Lake,

FP-CCD GLD VERTEX GROUP Presenting by Tadashi Nagamine Tohoku University ILC VTX Ringberg Castle, May 2006.

Andrei Nomerotski 1 Andrei Nomerotski, University of Oxford for LCFI collaboration LCWS2008, 17 November 2008 Column Parallel CCD and Raw Charge Storage.

GGT-Electronics System design Alexander Kluge CERN-PH/ED April 3, 2006.

Andrei Nomerotski 1 Andrei Nomerotski, University of Oxford Ringberg Workshop, 8 April 2008 Pixels with Internal Storage: ISIS by LCFI.

3D CMOS monolithic 3-bit resolution pixel sensor with fast digital pipelined readout Olav Torheim, Yunan Fu, Christine Hu-Guo, Yann Hu, Marc Winter.

LHC1 & COOP September 1995 Report

Overview of the Data Acquisition Activities

APSEL6D Architecture, simulations and results

Iwaki System Readout Board User’s Guide

DCH FEE 28 chs DCH prototype FEE &

Large Area Endplate Prototype for the LC TPC

First Testbeam results

A 3D deep n-well CMOS MAPS for the ILC vertex detector

Vertex 2005 November 7-11, 2005 Chuzenji Lake, Nikko, Japan

Example of DAQ Trigger issues for the SoLID experiment

SVT detector electronics

FPCCD Vertex Detector for ILC

Yasuhiro Sugimoto KEK 17 R&D status of FPCCD VTX Yasuhiro Sugimoto KEK 17

FPCCD Vertex Detector for ILC

The CMS Tracking Readout and Front End Driver Testing

SVT detector electronics

TELL1 A common data acquisition board for LHCb

Perugia SuperB Workshop June 16-19, 2009

Presentation transcript:

Joel Goldstein, RAL 4th ECFA/DESY LC Workshop, 1/4/ Vertex Readout Joel Goldstein PPd, RAL 4 th ECFA/DESY LC Workshop DAQ Session 1 st April 2003

Joel Goldstein, RAL 4th ECFA/DESY LC Workshop, 1/4/ Outline 1.Vertex detector conceptual design 2.CP CCD technology option 3.Planned readout scheme 4.Other scenarios (More demanding TESLA environment used throughout)

Joel Goldstein, RAL 4th ECFA/DESY LC Workshop, 1/4/ The Vertex Detector 5 layers (15-60mm) ~ 0.1% X 0 per layer 20  m  20  m pixels 800 million channels Background rates force readout  –50  s for Layer 1 –250  s for Layer 2

Joel Goldstein, RAL 4th ECFA/DESY LC Workshop, 1/4/ Column Parallel CCDs Separate readout for each column Readout chip bump-bonded to CCD Chips contain: –Amplifiers –5-bit FADCs –Filters –Sparsification logic –Local memory

Joel Goldstein, RAL 4th ECFA/DESY LC Workshop, 1/4/ Detector Parameters Layer Radius /mm CCD L  W /mm CCDs /ladder No. of lad’s Clock /MHz RO Time /  s Bkgd kHits /train     

Joel Goldstein, RAL 4th ECFA/DESY LC Workshop, 1/4/ Ladder Readout Layer 1 read out 20 times per bunch train  50k z pixels Layer 2 read out 5 times per bunch train  31k z pixels –31 bits/4 bytes pixel address

Joel Goldstein, RAL 4th ECFA/DESY LC Workshop, 1/4/ DAQ Plan 4.4 billion pixels  5 bits = a lot of data! So, 1.Sparsify locally into clusters (2  2,…) 2.Store on chip 3.Readout during 200ms dead time 1.3 million hits = 20 Mbytes per bunch train

Joel Goldstein, RAL 4th ECFA/DESY LC Workshop, 1/4/ Detector Level DAQ

Joel Goldstein, RAL 4th ECFA/DESY LC Workshop, 1/4/ Front End Readout Chain

Joel Goldstein, RAL 4th ECFA/DESY LC Workshop, 1/4/ Other Scenarios NLC: Bkgd hits/train ~ 0.1  TESLA Readout in 8.3 ms dead time TESLA 800: 2  bunches/train Same CCD clock speed More capacity in readout? –Memory, datalinks etc. –Still to be looked at Active Pixels: Similar schemes feasible

Joel Goldstein, RAL 4th ECFA/DESY LC Workshop, 1/4/ Summary 800 MPixel CP CCD vertex detector Clustering and sparsification performed on readout chip ~10 Mbytes per bunch train per end Single interface card per end, outside tracking volume Minimal external connections –input control fibre, output data fibre, power Other technologies similar Testing of first CP CCDs and readout chips starting