Prof. Dr. Martin Brooke Bortecene Terlemez On-chip Learning Neural Network Hardware Implementation for Real-time Control Prof. Dr. Martin Brooke Bortecene Terlemez

Current Status Simulation Experiments Two frequency simulation Added noise simulation Experiments 1 second suppression Long runs

Simulation Setup Delay 1.5 ms Delay line error Unstable Combustion Model x u Software Simulation of Neural Network Chip

One Frequency Plant without Control

One Frequency Result f = 400Hz b = 

Two Frequency Results f = 400Hz 700Hz b =  The

10 % Added Noise Results f=400Hz z=0.005 b=1 Uncontrolled Engine Neural Network Controlled Engine f=400Hz z=0.005 b=1

Continuously Changing Plant Parameters (1 point/ second)

Continuously Changing Plant Parameters (50 points/ second)

Experimental Setup

Short run-time f = 400 Hz

Long run-time f = 400 Hz

Experimental Conclusions Suppression of Oscillation in less than few seconds. Continuous Adaptation.

Issues Competing technology status Controller Initialization General Purpose HW vs Dedicated HW Controller Initialization How to find optimum weights? How to set the weights?

Dedicated NN Hardware Serial Digital [1] Partially Parallel Digital [2] Fully Parallel Digital [3] Fully Parallel Analog [4]

References [1] Torsten Lehmann, Erik Bruun, and Casper Dietrich, “Mixed Analog/Digital Matrix-Vector Multiplier for Neural Network Synapses.” Analog Integrated Circuits and Signal Processing, 9, pp. 55-63, 1996. [2] Antonio J. Montalvo, Ronald S. Gyurcsik, and John J. Paulos, “An Analog VLSI Neural Network with On-Chip Perturbation Learning”, IEEE Journal of Solid-State Circuits, Vol. 32, No. 4, April 1997. [3] S. Neusser and B. Hofflinger, "Parallel Digital Neural Hardware for Controller Design", Mathematics and Computers in Simulation, Vol. 41, Pp. 149-160, 1996. [4] Maurizio Valle, Daniele D. Caviglia, and Ciacomo M. Bisio, “An Experimental Analog VLSI Neural Network with On-Chip Back-Propagation Learning”, Analog Integrated Circuits and Signal Processing, 9, pp. 231-245, 1996.

Time for One Forward Propagation Normalized speeds (Time: Number of Gate Delays)

(Area: Number of Transistors)

Today’s Technology - 0.35 mm CMOS Speed (ns) Chip Area (mm2)

Area and Time Requirement for 0.35-mm CMOS Process

Area and Time Estimation for 70-nm CMOS Process Speed (ns) Chip Area (mm2)

Area and Time Requirement for 70-nm CMOS Process

Controller Initialization How to find weights Simulation Is this good enough? Recorded training

Simulation Problem : Current chips are volatile Solution : FPGA

Recorded Simulation (current chip) Error Decrease Signal Random Sequence Error Decreases f = 400Hz z = 0.0 b = 0.1

Controller Initialization How to set weights Recorded simulation/training (current chips) permanent analog weight Digital weight storage (FPGA, custom)

Permanent Weight Storage EEPROM - FLASH Kah ng and S ze (?) FG De vi ce s and Circuits log 1989 1999 ET A N Br oo ke , et.al Shib ata/ Ohm i Ya STL AF G Ada pt iv e Ret ina ISD- Voic Re co rd er Digital Non-volitile Memories 1967 ...... .

Past EEPROM NN Permanent weight version of current chip

Permanent Analog Weight: Floating-Gate MOS (n-well) Regular CMOS Floating Gate MOS

RWC module with Floating-Gate MOS

Digital Weight Storage Custom digital chips Field Programmable Gate Arrays (FPGA)

Custom digital chips 13 bit programmable DAC 6-8 bits probably enough Expensive/slow to develop

Field Programmable Gate Arrays (FPGA) Reconfigurable Flexible Low-cost design cycle 1992: First ANN on FPGA 30 of XC3090 (8000 gates each) used Each neuron with 14 synapses:2 FPGA + 1 EPROM Today: very high density FPGAs with partial dynamic reconfiguration made possible ( >3 million gates)

RRANN Run-time Reconfigurable Artificial Neural Networks (RRANN) Time sharing the limited computing resource.

Conclusion FPGA technology ready Plan to attempt weight initialization Faster development Plan to adapt current test setups Plan to attempt weight initialization Recorded simulation/ training (current chips) Digital weights (FPGA)