1. DEFENSE EXAMINATION GEORGIA TECH ECE P. 1 Fully Parallel Learning Neural Network Chip for Real-time Control Jin Liu Advisor: Dr. Martin Brooke Dissertation Defense Examination May 25th, 1999

2. DEFENSE EXAMINATION GEORGIA TECH ECE P. 2 Overview Introduction to Neural Network (NN) Review of NN Hardware Implementations Random-Weight-Change Algorithm and Chip Hardware Test and Modification Software Simulation on Combustion Control NN Chip Control of Simulated Combustion Instability New Generation of the NN Chip Conclusion and Future Work

3. DEFENSE EXAMINATION GEORGIA TECH ECE P. 3 A Neuron Out In1 In2 In3 w2 w3 w1 Out = f ( In1*w1 + In2 *w2 + In3*w3)

4. DEFENSE EXAMINATION GEORGIA TECH ECE P. 4 A Neural Network Out In3 In2 In1 A Neuron Weights are updated according to learning algorithm.

5. DEFENSE EXAMINATION GEORGIA TECH ECE P. 5 Review of Neural Network Hardware Serial Digital [1] Partially Parallel Digital [2] Fully Parallel Digital [3] Fully Parallel Analog [4] [1] Gensuke Goto, Tomio Sato, Masao Nakajima, and Takao Sukemura, "A 54 x 54-b Regularly Structured Tree Multiplier", IEEE Journal of Solid-state Circuits, Vol. 27, No. 9, September, 1992. [2] Moritoshi Yasunaga, Noboru Masuda, Masayoshi Yagyu, Mitsue Asai, Katsunari Shibata, Mitsue Ooyama, Minoru Yamada, Takahiro Sakaguchi, and Masashi Hashimoto, "A Self-Learning Digital Neural Network Using Wafer-Scale LSI", IEEE Journal of Solid-state Circuits, Vol. 28, No. 2, February, 1993. [3] S. Neusser and B. Hofflinger, "Parallel Digital Neural Hardware for Controller Design", Mathematics and Computers in Simulation, Vol. 41, Pp. 149-160, 1996. [4] Kenichi Hirotsu and Martin Brooke, “An analog neural network chip with random weight change learning algorithm”, Proceedings of the International Joint Conference on Neural Networks, pp. 3031-3034, October 1993.

6. DEFENSE EXAMINATION GEORGIA TECH ECE P. 6 Time for One Forward Propagation (Time: Number of Gate Delay) Network Size Implementations

7. DEFENSE EXAMINATION GEORGIA TECH ECE P. 7 Plot

8. DEFENSE EXAMINATION GEORGIA TECH ECE P. 8 Area (Area: Number of Transistors) Network Size Implementations

9. DEFENSE EXAMINATION GEORGIA TECH ECE P. 9 Plot

10. DEFENSE EXAMINATION GEORGIA TECH ECE P. 10 Efficiency

11. DEFENSE EXAMINATION GEORGIA TECH ECE P. 11 Area and Time Requirement for 0.35-  m CMOS Process

12. DEFENSE EXAMINATION GEORGIA TECH ECE P. 12 Estimation of the Speed of 70-nm CMOS Process The 31 Stage Ring Oscillator Frequency: 497 MHz (Gate Delay 0.0649 ns) Process Frequency

13. DEFENSE EXAMINATION GEORGIA TECH ECE P. 13 Area and Time Requirement for 70-nm CMOS Process

14. DEFENSE EXAMINATION GEORGIA TECH ECE P. 14 Learning Algorithm - Random Weight Change (RWC) Target Starting Point

15. DEFENSE EXAMINATION GEORGIA TECH ECE P. 15 Random-Weight-Change Chip (Modified)

16. DEFENSE EXAMINATION GEORGIA TECH ECE P. 16 Chip Architecture - Block Diagram Synapse Neurons Input Output

17. DEFENSE EXAMINATION GEORGIA TECH ECE P. 17 Cell Schematics Cell

18. DEFENSE EXAMINATION GEORGIA TECH ECE P. 18 Weight Updating

19. DEFENSE EXAMINATION GEORGIA TECH ECE P. 19 Multiplier Function

20. DEFENSE EXAMINATION GEORGIA TECH ECE P. 20 Clocking Scheme for Learning

21. DEFENSE EXAMINATION GEORGIA TECH ECE P. 21 Shift Registers for Shifting Random Numbers Weight Increasing and Decreasing Biasing for Multiplier to Give Correct Transfer Function Training One Weight to Desired Value Training Two-input/One-output Network as an Inverter Hardware Tests

22. DEFENSE EXAMINATION GEORGIA TECH ECE P. 22 Test Setup

23. DEFENSE EXAMINATION GEORGIA TECH ECE P. 23 Weight Updating

24. DEFENSE EXAMINATION GEORGIA TECH ECE P. 24 Multiplier

25. DEFENSE EXAMINATION GEORGIA TECH ECE P. 25 Training One Weight 1.5v 5v w To train one weight so that the neuron gives a desired output value, given a fixed input:

26. DEFENSE EXAMINATION GEORGIA TECH ECE P. 26 Capacitor Coupling Trial

27. DEFENSE EXAMINATION GEORGIA TECH ECE P. 27 Training with 01/10 Pairs

28. DEFENSE EXAMINATION GEORGIA TECH ECE P. 28 Training with Random Numbers

29. DEFENSE EXAMINATION GEORGIA TECH ECE P. 29 Two Input Inverter w1 1 0/1 1/0 w2 ‘0’: 1v ‘1’: 2v To train a two-weight network, the desired output inverses one of the inputs, with the other as a reference voltage:

30. DEFENSE EXAMINATION GEORGIA TECH ECE P. 30 Computer Collected Data

31. DEFENSE EXAMINATION GEORGIA TECH ECE P. 31 Error Signal

32. DEFENSE EXAMINATION GEORGIA TECH ECE P. 32 Initial Learning Process

33. DEFENSE EXAMINATION GEORGIA TECH ECE P. 33 More Data for Different High/Low Values 0.5-1.5

34. DEFENSE EXAMINATION GEORGIA TECH ECE P. 34 Continuously Adjusting Process

35. DEFENSE EXAMINATION GEORGIA TECH ECE P. 35 Summary of Preliminary Hardware Test The RWC chip learned to implement an inverter function, within around 140 iterations. It maintains the desired performance by continuously adjusting on-line.

36. DEFENSE EXAMINATION GEORGIA TECH ECE P. 36 Combustion Instability Control - Simulation Results Review Simulated Neural Net and Combustion One-frequency Results Multi-frequency Results Parameter Variation Results Added Noise Results

37. DEFENSE EXAMINATION GEORGIA TECH ECE P. 37 Simulation Setup Delay 1.5 ms Delay line error Unstable Combustion Model xu Software Simulation of Neural Network Chip

38. DEFENSE EXAMINATION GEORGIA TECH ECE P. 38 One Frequency Result f = 400Hz b = 

39. DEFENSE EXAMINATION GEORGIA TECH ECE P. 39 One Frequency Plant without Control

40. DEFENSE EXAMINATION GEORGIA TECH ECE P. 40 Two-Frequency Results f = 400Hz 700Hz b = 

41. DEFENSE EXAMINATION GEORGIA TECH ECE P. 41 Parameter Variation Results f = 400-600Hz  = 0-0.008 b = 1-100 Rate=1/secRate=50/sec

42. DEFENSE EXAMINATION GEORGIA TECH ECE P. 42 10 % Added Noise Results Uncontrolled Engine Neural Network Controlled Engine f=400Hz  =0.005 b=1

43. DEFENSE EXAMINATION GEORGIA TECH ECE P. 43 Neural Network Chip Control of Combustion Instability Delay 1.5ms Delay line 2.5 ms 8 taps error  400Hz  x  x 2 /b -1)x+  2 x=u... xu

44. DEFENSE EXAMINATION GEORGIA TECH ECE P. 44 Experiment Setup

45. DEFENSE EXAMINATION GEORGIA TECH ECE P. 45 The Test Box

46. DEFENSE EXAMINATION GEORGIA TECH ECE P. 46 Experimental Result f = 400Hz  = 0.0 b = 0.1

47. DEFENSE EXAMINATION GEORGIA TECH ECE P. 47 More Results

48. DEFENSE EXAMINATION GEORGIA TECH ECE P. 48 More Results

49. DEFENSE EXAMINATION GEORGIA TECH ECE P. 49 Details of Initial Oscillation Suppression Error Decreases

50. DEFENSE EXAMINATION GEORGIA TECH ECE P. 50 Details of the Continuously Adjusting Process Error Increases Error Decreases

51. DEFENSE EXAMINATION GEORGIA TECH ECE P. 51 Experiments with Longer Running Time

52. DEFENSE EXAMINATION GEORGIA TECH ECE P. 52 Experiments with Bigger Damping Factor  =0.001

53. DEFENSE EXAMINATION GEORGIA TECH ECE P. 53 Experiments with Bigger Damping Factor  =0.002

54. DEFENSE EXAMINATION GEORGIA TECH ECE P. 54 Summary of NN Chip Control of Simulated Combustion Instability The NN chip can successfully suppress the combustion instabilities within around 1 sec. The NN chip continuously adjusts on-line to limit the engine output to be within a small magnitude. –I/O card delay and engine simulation delay 30 times longer than real time Weight leakage –Fixed learning step size

55. DEFENSE EXAMINATION GEORGIA TECH ECE P. 55 Improved Neural Network Chip in 0.35-  m Process Seven Time More Neuron Cells Two layers Each layer has 30 inputs instead of 10 Totally 720 neurons instead of 100 Adaptive Learning Step Size Capacitor charge sharing scheme Current charging and discharging scheme Partitioned Error Feedback Synchronized Learning, without stopping the clocks

56. DEFENSE EXAMINATION GEORGIA TECH ECE P. 56 New Chip

57. DEFENSE EXAMINATION GEORGIA TECH ECE P. 57 Chip Architecture - Block Diagram

58. DEFENSE EXAMINATION GEORGIA TECH ECE P. 58 Cell Schematics Cell

59. DEFENSE EXAMINATION GEORGIA TECH ECE P. 59 Full Chip Spice Simulation after Parasitic Extraction Shift Register Weight Updating Current Outputs at Pads Clocking Scheme

60. DEFENSE EXAMINATION GEORGIA TECH ECE P. 60 Shift Register X=1ms First 0 to 1 at sh_in X=1.48ms First 0 to 1 at sh_out_1r 24 cycles of delay X=15.4ms First 0 to 1 at sh_out_end 720 cycles of delay

61. DEFENSE EXAMINATION GEORGIA TECH ECE P. 61 Weight Updating Shifted in voltage Weights

62. DEFENSE EXAMINATION GEORGIA TECH ECE P. 62 Output Currents at Pads

63. DEFENSE EXAMINATION GEORGIA TECH ECE P. 63 Clocking Scheme for Learning Sh_in data 11 22  _learn  _random for three sub-nets One clocking cycle is 20  s

64. DEFENSE EXAMINATION GEORGIA TECH ECE P. 64 Conclusion Extensive software simulations to provide a solution for real-time control using the RWC algorithm, with direct feedback scheme Successful application of the analog neural network chip to control simulated dynamic, nonlinear system Improved chip resulted from the extensive hardware experiments Automated test method and system

65. DEFENSE EXAMINATION GEORGIA TECH ECE P. 65 Future Works Acoustic Oscillation Suppression Test of the New Chip Real Combustion System Control Third Generation Chip (~Million Weights )

66. DEFENSE EXAMINATION GEORGIA TECH ECE P. 66 Acoustic Oscillation Setup