© Digital Integrated Circuits 2nd Memories Digital Integrated Circuits A Design Perspective SemiconductorMemories Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic December 20, 2002

© Digital Integrated Circuits 2nd Memories Chapter Overview  Memory Classification  Memory Architectures  The Memory Core  Periphery  Reliability  Case Studies

© Digital Integrated Circuits 2nd Memories Semiconductor Memory Classification Read-Write Memory Non-Volatile Read-Write Memory Read-Only Memory EPROM E 2 PROM FLASH Random Access Non-Random Access SRAM DRAM Mask-Programmed Programmable (PROM)‏ FIFO Shift Register CAM LIFO

© Digital Integrated Circuits 2nd Memories Memory Timing: Definitions

© Digital Integrated Circuits 2nd Memories Memory Architecture: Decoders Word 0 Word 1 Word 2 WordN 2 2 N 2 1 Storage cell M bitsM N words S 0 S 1 S 2 S N 2 2 A 0 A 1 A K 2 1 K 5 log 2 N S N 2 1 Word 0 Word 1 Word 2 WordN 2 2 N 2 1 Storage cell S 0 Input-Output (M bits)‏ Intuitive architecture for N x M memory Too many select signals: N words == N select signals K = log 2 N Decoder reduces the number of select signals Input-Output (M bits)‏ Decoder

© Digital Integrated Circuits 2nd Memories Array-Structured Memory Architecture Problem: ASPECT RATIO or HEIGHT >> WIDTH Amplify swing to rail-to-rail amplitude Selects appropriate word

© Digital Integrated Circuits 2nd Memories Hierarchical Memory Architecture Advantages: 1. Shorter wires within blocks 2. Block address activates only 1 block => power savings

© Digital Integrated Circuits 2nd Memories Memory Timing: Approaches DRAM Timing Multiplexed Adressing SRAM Timing Self-timed

© Digital Integrated Circuits 2nd Memories Read-Only Memory Cells WL BL WL BL 1 WL BL WL BL WL BL 0 V DD WL BL GND Diode ROMMOS ROM 1MOS ROM 2

© Digital Integrated Circuits 2nd Memories MOS NOR ROM WL[0] GND BL[0] WL[1] WL[2] WL[3] V DD BL[1] Pull-up devices BL[2]BL[3] GND

© Digital Integrated Circuits 2nd Memories MOS NOR ROM Layout Programmming using the Active Layer Only Polysilicon Metal1 Diffusion Metal1 on Diffusion Cell (9.5 x 7 )‏

© Digital Integrated Circuits 2nd Memories MOS NAND ROM All word lines high by default with exception of selected row WL[0] WL[1] WL[2] WL[3] V DD Pull-up devices BL[3]BL[2]BL[1]BL[0]

© Digital Integrated Circuits 2nd Memories MOS NAND ROM Layout No contact to VDD or GND necessary; Loss in performance compared to NOR ROM drastically reduced cell size Polysilicon Diffusion Metal1 on Diffusion Cell (8 x 7 )‏ Programmming using the Metal-1 Layer Only

© Digital Integrated Circuits 2nd Memories NAND ROM Layout Cell (5 x 6 )‏ Polysilicon Threshold-altering implant Metal1 on Diffusion Programmming using Implants Only

© Digital Integrated Circuits 2nd Memories Decreasing Word Line Delay

© Digital Integrated Circuits 2nd Memories Precharged MOS NOR ROM PMOS precharge device can be made as large as necessary, but clock driver becomes harder to design. WL[0] GND BL[0] WL[1] WL[2] WL[3] V DD BL[1] Precharge devices BL[2]BL[3] GND pre f

© Digital Integrated Circuits 2nd Memories Non-Volatile Memories The Floating-gate transistor (FAMOS) ‏ Floating gate Source Substrate Gate Drain n + n +_ p t ox t Device cross-section Schematic symbol G S D

© Digital Integrated Circuits 2nd Memories Floating-Gate Transistor Programming 0 V 2 5 V 0 V DS Removing programming voltage leaves charge trapped 5 V V 5 V DS Programming results in higherV T. 20 V 10 V5 V 20 V DS Avalanche injection

© Digital Integrated Circuits 2nd Memories A “Programmable-Threshold” Transistor

© Digital Integrated Circuits 2nd Memories FLOTOX EEPROM Floating gate Source Substrate p Gate Drain n 1 n 1 FLOTOX transistor Fowler-Nordheim I-V characteristic 20–30 nm 10 nm -10 V 10 V I V GD

© Digital Integrated Circuits 2nd Memories EEPROM Cell WL BL V DD Absolute threshold control is hard Unprogrammed transistor might be depletion  2 transistor cell

© Digital Integrated Circuits 2nd Memories Flash EEPROM Control gate erasure p-substrate Floating gate Thin tunneling oxide n 1 source n 1 drain programming Many other options …

© Digital Integrated Circuits 2nd Memories Basic Operations in a NOR Flash Memory― Erase

© Digital Integrated Circuits 2nd Memories Basic Operations in a NOR Flash Memory― Write

© Digital Integrated Circuits 2nd Memories Basic Operations in a NOR Flash Memory― Read

© Digital Integrated Circuits 2nd Memories NAND Flash Memory Unit Cell Word line(poly)‏ Source line (Diff. Layer)‏ Courtesy Toshiba

© Digital Integrated Circuits 2nd Memories NAND Flash Memory Word linesSelect transistor Bit line contactSource line contact Active area STI Courtesy Toshiba

© Digital Integrated Circuits 2nd Memories Characteristics of State-of-the-art NVM

© Digital Integrated Circuits 2nd Memories Read-Write Memories (RAM) ‏  STATIC (SRAM)‏  DYNAMIC (DRAM)‏ Data stored as long as supply is applied Large (6 transistors/cell)‏ Fast Differential Periodic refresh required Small (1-3 transistors/cell)‏ Slower Single Ended

© Digital Integrated Circuits 2nd Memories 6-transistor CMOS SRAM Cell WL BL V DD M 5 M 6 M 4 M 1 M 2 M 3 BL Q Q

© Digital Integrated Circuits 2nd Memories 6T-SRAM — Layout V DD GND Q Q WL BL M1 M3 M4M2 M5M6

© Digital Integrated Circuits 2nd Memories Resistance-load SRAM Cell Static power dissipation -- Want R L large Bit lines precharged to V DD to address t p problem M 3 R L R L V DD WL QQ M 1 M 2 M 4 BL

© Digital Integrated Circuits 2nd Memories SRAM Characteristics

© Digital Integrated Circuits 2nd Memories 1-Transistor DRAM Cell Write: C S is charged or discharged by asserting WL and BL. Read: Charge redistribution takes places between bit line and storage capacitance Voltage swing is small; typically around 250 mV.  V BL V PRE –V BIT V PRE – C S C S C BL == V

© Digital Integrated Circuits 2nd Memories DRAM Cell Observations  1T DRAM requires a sense amplifier for each bit line, due to charge redistribution read-out.  DRAM memory cells are single ended in contrast to SRAM cells.  The read-out of the 1T DRAM cell is destructive; read and refresh operations are necessary for correct operation.  Unlike 3T cell, 1T cell requires presence of an extra capacitance that must be explicitly included in the design.  When writing a “1” into a DRAM cell, a threshold voltage is lost. This charge loss can be circumvented by bootstrapping the word lines to a higher value than V DD

© Digital Integrated Circuits 2nd Memories Sense Amp Operation D V(1)‏ V V(0)‏ t V PRE V BL Sense amp activated Word line activated

© Digital Integrated Circuits 2nd Memories 1-T DRAM Cell Uses Polysilicon-Diffusion Capacitance Expensive in Area M 1 word line Diffused bit line Polysilicon gate Polysilicon plate Capacitor Cross-section Layout Metal word line Poly SiO 2 Field Oxide n + n + Inversion layer induced by plate bias Poly

© Digital Integrated Circuits 2nd Memories Periphery  Decoders  Sense Amplifiers  Input/Output Buffers  Control / Timing Circuitry

© Digital Integrated Circuits 2nd Memories Row Decoders Collection of 2 M complex logic gates Organized in regular and dense fashion (N)AND Decoder NOR Decoder

© Digital Integrated Circuits 2nd Memories Hierarchical Decoders A 2 A 2 A 2 A 3 WL 0 A 2 A 3 A 2 A 3 A 2 A 3 A 3 A 3 A 0 A 0 A 0 A 1 A 0 A 1 A 0 A 1 A 0 A 1 A 1 A 1 1 Multi-stage implementation improves performance NAND decoder using 2-input pre-decoders

© Digital Integrated Circuits 2nd Memories Dynamic Decoders Precharge devices V DD  GND WL A 0 A 0 GND A 1 A 1  WL 3 A 0 A 0 A 1 A V DD V V V 2-input NOR decoder 2-input NAND decoder

© Digital Integrated Circuits 2nd Memories 4-input pass-transistor based column decoder Advantages: speed (t pd does not add to overall memory access time)‏ Only one extra transistor in signal path Disadvantage: Large transistor count 2-input NOR decoder A 0 S 0 BL A 1 S 1 S 2 S 3 D

© Digital Integrated Circuits 2nd Memories 4-to-1 tree based column decoder Number of devices drastically reduced Delay increases quadratically with # of sections; prohibitive for large decoders buffers progressive sizing combination of tree and pass transistor approaches Solutions: BL D A 0 A 0 A 1 A 1

© Digital Integrated Circuits 2nd Memories Sense Amplifiers t p C  V  I av = make  V as small as possible smalllarge Idea: Use Sense Amplifer output input s.a. small transition

© Digital Integrated Circuits 2nd Memories Differential Sense Amplifier Directly applicable to SRAMs M 4 M 1 M 5 M 3 M 2 V DD bit SE Out y

© Digital Integrated Circuits 2nd Memories Differential Sensing ― SRAM

© Digital Integrated Circuits 2nd Memories Latch-Based Sense Amplifier (DRAM) ‏ Initialized in its meta-stable point with EQ Once adequate voltage gap created, sense amp enabled with SE Positive feedback quickly forces output to a stable operating point. EQ V DD BL SE

© Digital Integrated Circuits 2nd Memories Charge-Redistribution Amplifier Concept M 2 M 3 M 1 V L V S V ref C small C large Transient Response

© Digital Integrated Circuits 2nd Memories Charge-Redistribution Amplifier― EPROM SE V DD WLC Load Cascode device Column decoder EPROM array BL WL V casc Out C out C col C BL M 1 M 2 M 3 M 4

© Digital Integrated Circuits 2nd Memories Single-to-Differential Conversion How to make a good V ref ?

© Digital Integrated Circuits 2nd Memories Open bitline architecture with dummy cells C S C S C S C S BLL LL 1 L 0 R 0 C S R 1 C S L … … BLR V DD SE EQ Dummy cell

© Digital Integrated Circuits 2nd Memories DRAM Read Process with Dummy Cell V BL t (ns) ‏ reading V SE EQWL t (ns) ‏ control signals V BL t (ns) ‏ reading 1

© Digital Integrated Circuits 2nd Memories Voltage Regulator - + V DD V REF V bias M drive M V DL V V REF Equivalent Model

© Digital Integrated Circuits 2nd Memories Charge Pump

© Digital Integrated Circuits 2nd Memories DRAM Timing

© Digital Integrated Circuits 2nd Memories RDRAM Architecture memory array mux/demux network Data bus Clocks Column Row demux packet dec. Bus k k 3 l demux

© Digital Integrated Circuits 2nd Memories Address Transition Detection DELAY t d A 0 t d A 1 t d A N 2 1 V DD ATD …

© Digital Integrated Circuits 2nd Memories Reliability and Yield

© Digital Integrated Circuits 2nd Memories Sensing Parameters in DRAM From [Itoh01] 4K K1M16M256M4G64G Memory Capacity (bits/chip)‏ C D, Q S, C S, V DD, V smax C D(1F)‏ C S Q S(1C)‏ V smax(mv)‏ V DD(V)‏ Q S 5 C S V DD /2 V smax 5 Q S /(C S 1 C D )‏

© Digital Integrated Circuits 2nd Memories Noise Sources in 1T DRam C cross electrode a -particles leakage C S WL BL substrate Adjacent BL C WBL

© Digital Integrated Circuits 2nd Memories Open Bit-line Architecture —Cross Coupling Sense Amplifier C WL 1 BL C C WBL C CC WL 0 C C BL CC WL D D 0 1 BL EQ

© Digital Integrated Circuits 2nd Memories Folded-Bitline Architecture

© Digital Integrated Circuits 2nd Memories Transposed-Bitline Architecture

© Digital Integrated Circuits 2nd Memories Alpha-particles (or Neutrons) ‏ 1 Particle ~ 1 Million Carriers WL BL V DD n 1 a -particle SiO

© Digital Integrated Circuits 2nd Memories Yield Yield curves at different stages of process maturity (from [Veendrick92])‏

© Digital Integrated Circuits 2nd Memories Redundancy Memory Array Column Decoder Row Decoder Redundant rows Redundant columns Row Address Column Address Fuse Bank :

© Digital Integrated Circuits 2nd Memories Error-Correcting Codes Example: Hamming Codes with e.g. B3 Wrong = 3

© Digital Integrated Circuits 2nd Memories Redundancy and Error Correction

© Digital Integrated Circuits 2nd Memories Sources of Power Dissipation in Memories PERIPHERY ROW DEC selected non-selected CHIP COLUMN DEC nC DE V INT f mC DE V INT f C PT V INT f I DCP ARRAY m n m(n 2 1)i hld mi act V DD V SS I DD 5S C i D V i f 1S I DCP From [Itoh00]

© Digital Integrated Circuits 2nd Memories Data Retention in SRAM (A)‏ SRAM leakage increases with technology scaling

© Digital Integrated Circuits 2nd Memories Suppressing Leakage in SRAM SRAM cell SRAM cell SRAM cell V DD,int V DD V V DDL V SS,int sleep SRAM cell SRAM cell SRAM cell V DD,int sleep low-threshold transistor Reducing the supply voltage Inserting Extra Resistance

© Digital Integrated Circuits 2nd Memories Data Retention in DRAM From [Itoh00]

© Digital Integrated Circuits 2nd Memories Case Studies  Programmable Logic Array  SRAM  Flash Memory

© Digital Integrated Circuits 2nd Memories PLA versus ROM  Programmable Logic Array structured approach to random logic “two level logic implementation” NOR-NOR (product of sums)‏ NAND-NAND (sum of products)‏ IDENTICAL TO ROM!  Main difference ROM: fully populated PLA: one element per minterm Note: Importance of PLA’s has drastically reduced 1.slow 2.better software techniques (mutli-level logic synthesis)‏ But …

© Digital Integrated Circuits 2nd Memories Programmable Logic Array GND V DD V X 0 X 0 X 1 f 0 f 1 X 1 X 2 X 2 AND-planeOR-plane Pseudo-NMOS PLA

© Digital Integrated Circuits 2nd Memories Dynamic PLA GND V DD V X 0 X 0 X 1 f 0 f 1 X 1 X 2 X 2 AND f f OR f f AND-planeOR-plane

© Digital Integrated Circuits 2nd Memories Clock Signal Generation for self-timed dynamic PLA f t pre t eval f AND f f f f OR f (a) Clock signals(b) Timing generation circuitry Dummy AND row

© Digital Integrated Circuits 2nd Memories PLA Layout

© Digital Integrated Circuits 2nd Memories 4 Mbit SRAM Hierarchical Word-line Architecture

© Digital Integrated Circuits 2nd Memories Bit-line Circuitry Bit-line load Block select ATD BEQ LocalWL Memory cell I/O line I/O B/T CD Sense amplifier CD I/O B/T

© Digital Integrated Circuits 2nd Memories Sense Amplifier (and Waveforms) ‏ BS I/OI/O DATA Block selectATD BSSA BS SEQ De i I/O Lines Address Data-cut ATD BEQ SEQ DATA Vdd GND SA, SA Vdd GND

© Digital Integrated Circuits 2nd Memories 1 Gbit Flash Memory From [Nakamura02]

© Digital Integrated Circuits 2nd Memories Writing Flash Memory Read level (4.5 V)‏ Number of cells V1V2V Vt of memory cells 3V4V Evolution of thresholds Final Distribution From [Nakamura02]

© Digital Integrated Circuits 2nd Memories 125mm 2 1Gbit NAND Flash Memory 10.7mm 11.7mm 2kB Page buffer & cacheCharge pump bit lines 32 word lines x 1024 blocks From [Nakamura02]

© Digital Integrated Circuits 2nd Memories 125mm 2 1Gbit NAND Flash Memory  Technology 0.13  m p-sub CMOS triple-well 1poly, 1polycide, 1W, 2Al  Cell size  m2  Chip size 125.2mm2  Organization 2112 x 8b x 64 page x 1k block  Power supply 2.7V-3.6V  Cycle time 50ns  Read time 25  s  Program time 200  s / page  Erase time 2ms / block  Technology 0.13  m p-sub CMOS triple-well 1poly, 1polycide, 1W, 2Al  Cell size  m2  Chip size 125.2mm2  Organization 2112 x 8b x 64 page x 1k block  Power supply 2.7V-3.6V  Cycle time 50ns  Read time 25  s  Program time 200  s / page  Erase time 2ms / block From [Nakamura02]

© Digital Integrated Circuits 2nd Memories Semiconductor Memory Trends (up to the 90’s) ‏ Memory Size as a function of time: x 4 every three years

© Digital Integrated Circuits 2nd Memories Semiconductor Memory Trends (updated) ‏ From [Itoh01]

© Digital Integrated Circuits 2nd Memories Trends in Memory Cell Area From [Itoh01]

© Digital Integrated Circuits 2nd Memories Semiconductor Memory Trends Technology feature size for different SRAM generations