1. © Digital Integrated Circuits 2nd Memories Digital Integrated Circuits A Design Perspective SemiconductorMemories Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic December 20, 2002

2. © Digital Integrated Circuits 2nd Memories Chapter Overview  Memory Classification  Memory Architectures  The Memory Core  Periphery  Reliability  Case Studies

3. © Digital Integrated Circuits 2nd Memories Memory Classification  Size  Speed (timing)  Technology (CMOS, bipolar)  Function (ROM, RWM)  Volatility  Access (random, serial)  Application

4. © Digital Integrated Circuits 2nd Memories Semiconductor Memory Classification Read-Write Memory Non-Volatile Read-Write Memory Read-Only Memory EPROM E 2 PROM FLASH Random Access Non-Random Access SRAM DRAM Mask-Programmed Programmable (PROM) FIFO Shift Register CAM LIFO

5. © Digital Integrated Circuits 2nd Memories Memory Timing: Definitions

6. © Digital Integrated Circuits 2nd Memories Memory Timing: Definitions  Read-access time: delay between the read request and the moment the data is available at the output.  Write-access time: delay between the write request and the writing of the input data into the memory.  Cycle time: the minimum time required between successive reads (or writes).

7. © Digital Integrated Circuits 2nd Memories Second Level Cache (SRAM) A Typical Memory Hierarchy Control Datapath Secondary Memory (Disk) On-Chip Components RegFile Main Memory (DRAM) Data Cache Instr Cache ITLB DTLB eDRAM Speed (ns):.1’s 1’s 10’s 100’s 1,000’s Size (bytes): 100’s K’s 10K’s M’s T’s Cost: highest lowest  By taking advantage of the principle of locality: l Present the user with as much memory as is available in the cheapest technology. l Provide access at the speed offered by the fastest technology.

8. © Digital Integrated Circuits 2nd Memories Memory Architecture  A memory of N words, each one M bits wide, needs one select bit to identify the word.  If the number of words is high (f.i. N=10 6 or N=2 20 ) we need too many select lines.  A memory word is selected from a decoder where encode addresses enter: N=2 k (in the exemple k=20).

9. © Digital Integrated Circuits 2nd Memories Memory Architecture: Decoders Word 0 Word 1 Word 2 WordN - 2 N - 1 Storage cell M bitsM N words S 0 S 1 S 2 S N - 2 A 0 A 1 A K - 1 K = log 2 N S N - 1 Word 0 Word 1 Word 2 WordN - 2 N - 1 Storage cell S 0 Input-Output (M bits) Intuitive architecture for N x M memory Too many select signals: N words == N select signals K = log 2 N Decoder reduces the number of select signals Input-Output (M bits) Decoder

10. © Digital Integrated Circuits 2nd Memories Array-Structured Memory Architecture Problem: ASPECT RATIO or HEIGHT >> WIDTH Amplify swing to rail-to-rail amplitude Selects appropriate word

11. © Digital Integrated Circuits 2nd Memories Array-Structured Memory Architecture  The select line that enables a sigle row of cells is the word line.  The line that connects the cells in a single column to the I/O circuits is the bit line.  Reduced swing requires sense amplifiers.

12. © Digital Integrated Circuits 2nd Memories Hierarchical Memory Architecture Advantages: 1. Shorter wires within blocks 2. Block address activates only 1 block => power savings

13. © Digital Integrated Circuits 2nd Memories Block Diagram of 4 Mbit SRAM Subglobal row decoder Global row decoder Subglobal row decoder Block 30 Block 31 128 K Array Block 0 Block 1 Local row decoder [Hirose90]

14. © Digital Integrated Circuits 2nd Memories Contents-Addressable Memory Address Decoder I/O Buffers Commands 2 9 Validity Bits Priority Encoder Address Decoder I/O Buffers Commands 2 9 Validity Bits Priority Encoder

15. © Digital Integrated Circuits 2nd Memories Memory Timing: Approaches DRAM Timing Multiplexed Adressing SRAM Timing Self-timed

16. © Digital Integrated Circuits 2nd Memories Read-Only Memory Cells WL BL WL BL 1 WL BL WL BL WL BL 0 V DD WL BL GND Diode ROMMOS ROM 1MOS ROM 2

17. © Digital Integrated Circuits 2nd Memories MOS OR ROM WL[0] V DD BL[0] WL[1] WL[2] WL[3] V bias BL[1] Pull-down loads BL[2]BL[3] V DD

18. © Digital Integrated Circuits 2nd Memories MOS NOR ROM WL[0] GND BL[0] WL[1] WL[2] WL[3] V DD BL[1] Pull-up devices BL[2]BL[3] GND

19. © Digital Integrated Circuits 2nd Memories MOS NOR ROM Layout Programmming using the Active Layer Only Polysilicon Metal1 Diffusion Metal1 on Diffusion Cell (9.5 x 7 )

20. © Digital Integrated Circuits 2nd Memories MOS NOR ROM Layout Polysilicon Metal1 Diffusion Metal1 on Diffusion Cell (11 x 7 ) Programmming using the Contact Layer Only

21. © Digital Integrated Circuits 2nd Memories MOS NAND ROM All word lines high by default with exception of selected row WL[0] WL[1] WL[2] WL[3] V DD Pull-up devices BL[3]BL[2]BL[1]BL[0]

22. © Digital Integrated Circuits 2nd Memories MOS NAND ROM Layout No contact to VDD or GND necessary; Loss in performance compared to NOR ROM drastically reduced cell size Polysilicon Diffusion Metal1 on Diffusion Cell (8 x 7 ) Programmming using the Metal-1 Layer Only

23. © Digital Integrated Circuits 2nd Memories NAND ROM Layout Cell (5 x 6 ) Polysilicon Threshold-altering implant Metal1 on Diffusion Programmming using Implants Only

24. © Digital Integrated Circuits 2nd Memories Equivalent Transient Model for MOS NOR ROM  Word line parasitics  Wire capacitance and gate capacitance  Wire resistance (polysilicon)  Bit line parasitics  Resistance not dominant (metal)  Drain and Gate-Drain capacitance Model for NOR ROM V DD C bit r word c WL BL

25. © Digital Integrated Circuits 2nd Memories Equivalent Transient Model for MOS NAND ROM  Word line parasitics  Similar to NOR ROM  Bit line parasitics  Resistance of cascaded transistors dominates  Drain/Source and complete gate capacitance Model for NAND ROM V DD C L r word c c bit r WL BL

26. © Digital Integrated Circuits 2nd Memories Decreasing Word Line Delay

27. © Digital Integrated Circuits 2nd Memories Precharged MOS NOR ROM PMOS precharge device can be made as large as necessary, but clock driver becomes harder to design. WL[0] GND BL[0] WL[1] WL[2] WL[3] V DD BL[1] Precharge devices BL[2]BL[3] GND pre f

28. © Digital Integrated Circuits 2nd Memories Non-Volatile Memories The Floating-gate transistor (FAMOS) Floating gate Source Substrate Gate Drain n + n +_ p t ox t Device cross-section Schematic symbol G S D

29. © Digital Integrated Circuits 2nd Memories Floating-Gate Transistor Programming 0 V 2 5 V 0 V DS Removing programming voltage leaves charge trapped 5 V 2 2.5 V 5 V DS Programming results in higherV T. 20 V 10 V5 V 20 V DS Avalanche injection

30. © Digital Integrated Circuits 2nd Memories A “Programmable-Threshold” Transistor

31. © Digital Integrated Circuits 2nd Memories FLOTOX EEPROM Floating gate Source Substrate p Gate Drain n 1 n 1 FLOTOX transistor Fowler-Nordheim I-V characteristic 20–30 nm 10 nm -10 V 10 V I V GD

32. © Digital Integrated Circuits 2nd Memories EEPROM Cell WL BL V DD Absolute threshold control is hard Unprogrammed transistor might be depletion  2 transistor cell

33. © Digital Integrated Circuits 2nd Memories Flash EEPROM Control gate erasure p-substrate Floating gate Thin tunneling oxide n 1 source n 1 drain programming Many other options …

34. © Digital Integrated Circuits 2nd Memories Cross-sections of NVM cells EPROMFlash Courtesy Intel

35. © Digital Integrated Circuits 2nd Memories Basic Operations in a NOR Flash Memory― Erase

36. © Digital Integrated Circuits 2nd Memories Basic Operations in a NOR Flash Memory― Write

37. © Digital Integrated Circuits 2nd Memories Basic Operations in a NOR Flash Memory― Read

38. © Digital Integrated Circuits 2nd Memories NAND Flash Memory Unit Cell Word line(poly) Source line (Diff. Layer) Courtesy Toshiba

39. © Digital Integrated Circuits 2nd Memories NAND Flash Memory Word linesSelect transistor Bit line contactSource line contact Active area STI Courtesy Toshiba

40. © Digital Integrated Circuits 2nd Memories Characteristics of State-of-the-art NVM

41. © Digital Integrated Circuits 2nd Memories Read-Write Memories (RAM)  STATIC (SRAM)  DYNAMIC (DRAM) Data stored as long as supply is applied Large (6 transistors/cell) Fast Differential Periodic refresh required Small (1-3 transistors/cell) Slower Single Ended

42. © Digital Integrated Circuits 2nd Memories 6-transistor CMOS SRAM Cell WL BL V DD M 5 M 6 M 4 M 1 M 2 M 3 BL Q Q

43. © Digital Integrated Circuits 2nd Memories CMOS SRAM Analysis (Read Q=1)  Both bit lines are precharged high.  The word line is actvated: M 5 and M 6 are ON.  The read operation consists of leaving BL=1 and of discharging BL through M 1 - M 5.  The resistance of M 5 must be larger than that of M 1 to avoid the change of state of the cell (read disturb).  Alternatively, the bit lines can be precharged at V DD /2.

44. © Digital Integrated Circuits 2nd Memories CMOS SRAM Analysis (Read) WL BL V DD M 5 M 6 M 4 M 1 V V V BL Q = 1 Q = 0 C bit C

45. © Digital Integrated Circuits 2nd Memories CMOS SRAM Analysis (Read) 0 0 0.2 0.4 0.6 0.8 1 1.2 0.5 Voltage rise [V] 11.21.52 Cell Ratio (CR) 2.53 Voltage Rise (V)

46. © Digital Integrated Circuits 2nd Memories CMOS SRAM Analysis (Write Q=0)  When Q=1, a 0 is written in the cell by setting BL=0 e BL=1.  Due to the read-disturb condition the data has to be written through M 6.  Q must become lower than the threshold of M1.

47. © Digital Integrated Circuits 2nd Memories CMOS SRAM Analysis (Write) BL = 1 = 0 Q = 0 Q = 1 M 1 M 4 M 5 M 6 V DD V WL

48. © Digital Integrated Circuits 2nd Memories CMOS SRAM Analysis (Write) PR=W 4 /W 6

49. © Digital Integrated Circuits 2nd Memories Cell Sizing  Keeping cell size minimized is critical for large caches  Minimum sized pull down fets (M1 and M3)  Requires minimum width and longer than minimum channel length pass transistors (M5 and M6) to ensure proper CR  But sizing of the pass transistors increases capacitive load on the word lines and limits the current discharged on the bit lines both of which can adversely affect the speed of the read cycle  Minimum width and length pass transistors  Boost the width of the pull downs (M1 and M3)  Reduces the loading on the word lines and increases the storage capacitance in the cell – both are good! – but cell size may be slightly larger

50. © Digital Integrated Circuits 2nd Memories 6T-SRAM — Layout V DD GND Q Q WL BL M1 M3 M4M2 M5M6

51. © Digital Integrated Circuits 2nd Memories Resistance-load SRAM Cell Static power dissipation -- Want R L large Bit lines precharged to V DD to address t p problem M 3 R L R L V DD WL QQ M 1 M 2 M 4 BL A process variation is required

52. © Digital Integrated Circuits 2nd Memories SRAM Characteristics

53. © Digital Integrated Circuits 2nd Memories 3-Transistor DRAM Cell No constraints on device ratios Reads are non-destructive Value stored at node X when writing a “1” = V WWL -V Tn WWL BL1 M 1 X M 3 M 2 C S 2 RWL V DD V 2 V T D V V 2 V T BL2 1 X RWL WWL

54. © Digital Integrated Circuits 2nd Memories 3T-DRAM — Layout BL2BL1GND RWL WWL M3 M2 M1

55. © Digital Integrated Circuits 2nd Memories 1-Transistor DRAM Cell Write: C S is charged or discharged by asserting WL and BL. Read: Charge redistribution takes places between bit line and storage capacitance Voltage swing is small; typically around 250 mV.  V BL V PRE –V BIT V PRE – C S C S C BL + ------------ == V

56. © Digital Integrated Circuits 2nd Memories DRAM Cell Observations  1T DRAM requires a sense amplifier for each bit line, due to charge redistribution read-out.  DRAM memory cells are single ended in contrast to SRAM cells.  The read-out of the 1T DRAM cell is destructive; read and refresh operations are necessary for correct operation.  Unlike 3T cell, 1T cell requires presence of an extra capacitance that must be explicitly included in the design.  When writing a “1” into a DRAM cell, a threshold voltage is lost. This charge loss can be circumvented by bootstrapping the word lines to a higher value than V DD

57. © Digital Integrated Circuits 2nd Memories Sense Amp Operation D V(1) V V(0) t V PRE V BL Sense amp activated Word line activated

58. © Digital Integrated Circuits 2nd Memories 1-T DRAM Cell Uses Polysilicon-Diffusion Capacitance Expensive in Area M 1 word line Diffused bit line Polysilicon gate Polysilicon plate Capacitor Cross-section Layout Metal word line Poly SiO 2 Field Oxide n + n + Inversion layer induced by plate bias Poly

59. © Digital Integrated Circuits 2nd Memories SEM of poly-diffusion capacitor 1T-DRAM

60. © Digital Integrated Circuits 2nd Memories Advanced 1T DRAM Cells Cell Plate Si Capacitor Insulator Storage Node Poly 2nd Field Oxide Refilling Poly Si Substrate Trench Cell Stacked-capacitor Cell Capacitor dielectric layer Cell plate Word line Insulating Layer IsolationTransfer gate Storage electrode

61. © Digital Integrated Circuits 2nd Memories Static CAM Memory Cell

62. © Digital Integrated Circuits 2nd Memories CAM in Cache Memory Address Decoder Hit Logic CAM ARRAY Input Drivers TagHit Address SRAM ARRAY Sense Amps / Input Drivers DataR/W

63. © Digital Integrated Circuits 2nd Memories Periphery  Decoders  Sense Amplifiers  Input/Output Buffers  Control / Timing Circuitry

64. © Digital Integrated Circuits 2nd Memories Row Decoders Collection of 2 M complex logic gates Organized in regular and dense fashion (N)AND Decoder NOR Decoder

65. © Digital Integrated Circuits 2nd Memories Hierarchical Decoders A 2 A 2 A 2 A 3 WL 0 A 2 A 3 A 2 A 3 A 2 A 3 A 3 A 3 A 0 A 0 A 0 A 1 A 0 A 1 A 0 A 1 A 0 A 1 A 1 A 1 1 Multi-stage implementation improves performance NAND decoder using 2-input pre-decoders

66. © Digital Integrated Circuits 2nd Memories Dynamic Decoders Precharge devices V DD  GND WL 3 2 1 0 A 0 A 0 GND A 1 A 1  WL 3 A 0 A 0 A 1 A 1 2 1 0 V DD V V V 2-input NOR decoder 2-input NAND decoder

67. © Digital Integrated Circuits 2nd Memories 4-input pass-transistor based column decoder Advantages: speed (t pd does not add to overall memory access time) Only one extra transistor in signal path Disadvantage: Large transistor count 2-input NOR decoder A 0 S 0 BL 0 1 2 3 A 1 S 1 S 2 S 3 D

68. © Digital Integrated Circuits 2nd Memories 4-to-1 tree based column decoder Number of devices drastically reduced Delay increases quadratically with # of sections; prohibitive for large decoders buffers progressive sizing combination of tree and pass transistor approaches Solutions: BL 0 1 2 3 D A 0 A 0 A 1 A 1

69. © Digital Integrated Circuits 2nd Memories Decoder for circular shift-register

70. © Digital Integrated Circuits 2nd Memories Sense Amplifiers t p C  V  I av ----------------= make  V as small as possible smalllarge Idea: Use Sense Amplifer output input s.a. small transition

71. © Digital Integrated Circuits 2nd Memories Differential Sense Amplifier Directly applicable to SRAMs M 4 M 1 M 5 M 3 M 2 V DD bit SE Out y

72. © Digital Integrated Circuits 2nd Memories Differential Sensing ― SRAM

73. © Digital Integrated Circuits 2nd Memories Latch-Based Sense Amplifier (DRAM) Initialized in its meta-stable point with EQ Once adequate voltage gap created, sense amp enabled with SE Positive feedback quickly forces output to a stable operating point. EQ V DD BL SE

74. © Digital Integrated Circuits 2nd Memories Charge-Redistribution Amplifier Concept M 2 M 3 M 1 V L V S V ref C small C large Transient Response

75. © Digital Integrated Circuits 2nd Memories Charge-Redistribution Amplifier― EPROM SE V DD WLC Load Cascode device Column decoder EPROM array BL WL V casc Out C out C col C BL M 1 M 2 M 3 M 4

76. © Digital Integrated Circuits 2nd Memories Single-to-Differential Conversion How to make a good V ref ?

77. © Digital Integrated Circuits 2nd Memories Open bitline architecture with dummy cells C S C S C S C S BLL LL 1 L 0 R 0 C S R 1 C S L … … BLR V DD SE EQ Dummy cell

78. © Digital Integrated Circuits 2nd Memories DRAM Read Process with Dummy Cell 3 2 1 0 0123 V BL t (ns) reading 0 3 2 1 0 0123 V SE EQWL t (ns) control signals 3 2 1 0 0123 V BL t (ns) reading 1

79. © Digital Integrated Circuits 2nd Memories Voltage Regulator - + V DD V REF V bias M drive M V DL V V REF Equivalent Model

80. © Digital Integrated Circuits 2nd Memories Charge Pump

81. © Digital Integrated Circuits 2nd Memories DRAM Timing

82. © Digital Integrated Circuits 2nd Memories RDRAM Architecture memory array mux/demux network Data bus Clocks Column Row demux packet dec. Bus k k 3 l demux

83. © Digital Integrated Circuits 2nd Memories Address Transition Detection DELAY t d A 0 t d A 1 t d A N 2 1 V DD ATD …

84. © Digital Integrated Circuits 2nd Memories Reliability and Yield

85. © Digital Integrated Circuits 2nd Memories Sensing Parameters in DRAM From [Itoh01] 4K 10 100 1000 64K1M16M256M4G64G Memory Capacity (bits/chip) C D, Q S, C S, V DD, V smax C D(1F) C S Q S(1C) V smax(mv) V DD(V) Q S 5 C S V DD /2 V smax 5 Q S /(C S 1 C D )

86. © Digital Integrated Circuits 2nd Memories Noise Sources in 1T DRam C cross electrode a -particles leakage C S WL BL substrate Adjacent BL C WBL

87. © Digital Integrated Circuits 2nd Memories Open Bit-line Architecture —Cross Coupling Sense Amplifier C WL 1 BL C C WBL C CC WL 0 C C BL CC WL D D 0 1 BL EQ

88. © Digital Integrated Circuits 2nd Memories Folded-Bitline Architecture

89. © Digital Integrated Circuits 2nd Memories Transposed-Bitline Architecture

90. © Digital Integrated Circuits 2nd Memories Alpha-particles (or Neutrons) 1 Particle ~ 1 Million Carriers WL BL V DD n 1 a -particle SiO 2 1 1 1 1 1 1 2 2 2 2 2 2

91. © Digital Integrated Circuits 2nd Memories Yield Yield curves at different stages of process maturity (from [Veendrick92])

92. © Digital Integrated Circuits 2nd Memories Redundancy Memory Array Column Decoder Row Decoder Redundant rows Redundant columns Row Address Column Address Fuse Bank :

93. © Digital Integrated Circuits 2nd Memories Error-Correcting Codes Example: Hamming Codes with e.g. B3 Wrong 1 1 0 = 3

94. © Digital Integrated Circuits 2nd Memories Redundancy and Error Correction

95. © Digital Integrated Circuits 2nd Memories Sources of Power Dissipation in Memories PERIPHERY ROW DEC selected non-selected CHIP COLUMN DEC nC DE V INT f mC DE V INT f C PT V INT f I DCP ARRAY m n m(n 2 1)i hld mi act V DD V SS I DD 5S C i D V i f 1S I DCP From [Itoh00]

96. © Digital Integrated Circuits 2nd Memories Data Retention in SRAM (A) SRAM leakage increases with technology scaling

97. © Digital Integrated Circuits 2nd Memories Suppressing Leakage in SRAM SRAM cell SRAM cell SRAM cell V DD,int V DD V V DDL V SS,int sleep SRAM cell SRAM cell SRAM cell V DD,int sleep low-threshold transistor Reducing the supply voltage Inserting Extra Resistance

98. © Digital Integrated Circuits 2nd Memories Data Retention in DRAM From [Itoh00]

99. © Digital Integrated Circuits 2nd Memories Case Studies  Programmable Logic Array  SRAM  Flash Memory

100. © Digital Integrated Circuits 2nd Memories PLA versus ROM  Programmable Logic Array structured approach to random logic “two level logic implementation” NOR-NOR (product of sums) NAND-NAND (sum of products) IDENTICAL TO ROM!  Main difference ROM: fully populated PLA: one element per minterm Note: Importance of PLA’s has drastically reduced 1.slow 2.better software techniques (mutli-level logic synthesis) But …

101. © Digital Integrated Circuits 2nd Memories Programmable Logic Array GND V DD V X 0 X 0 X 1 f 0 f 1 X 1 X 2 X 2 AND-planeOR-plane Pseudo-NMOS PLA

102. © Digital Integrated Circuits 2nd Memories Dynamic PLA GND V DD V X 0 X 0 X 1 f 0 f 1 X 1 X 2 X 2 AND f f OR f f AND-planeOR-plane

103. © Digital Integrated Circuits 2nd Memories Clock Signal Generation for self-timed dynamic PLA f t pre t eval f AND f f f f OR f (a) Clock signals(b) Timing generation circuitry Dummy AND row

104. © Digital Integrated Circuits 2nd Memories PLA Layout

105. © Digital Integrated Circuits 2nd Memories 4 Mbit SRAM Hierarchical Word-line Architecture

106. © Digital Integrated Circuits 2nd Memories Bit-line Circuitry Bit-line load Block select ATD BEQ LocalWL Memory cell I/O line I/O B/T CD Sense amplifier CD I/O B/T

107. © Digital Integrated Circuits 2nd Memories Sense Amplifier (and Waveforms) BS I/OI/O DATA Block selectATD BSSA BS SEQ De i I/O Lines Address Data-cut ATD BEQ SEQ DATA Vdd GND SA, SA Vdd GND

108. © Digital Integrated Circuits 2nd Memories 1 Gbit Flash Memory From [Nakamura02]

109. © Digital Integrated Circuits 2nd Memories Writing Flash Memory Read level (4.5 V) Number of cells 10 0 0V1V2V Vt of memory cells 3V4V 10 2 4 6 8 Evolution of thresholds Final Distribution From [Nakamura02]

110. © Digital Integrated Circuits 2nd Memories 125mm 2 1Gbit NAND Flash Memory 10.7mm 11.7mm 2kB Page buffer & cacheCharge pump 16896 bit lines 32 word lines x 1024 blocks From [Nakamura02]

111. © Digital Integrated Circuits 2nd Memories 125mm 2 1Gbit NAND Flash Memory  Technology 0.13  m p-sub CMOS triple-well 1poly, 1polycide, 1W, 2Al  Cell size 0.077  m2  Chip size 125.2mm2  Organization 2112 x 8b x 64 page x 1k block  Power supply 2.7V-3.6V  Cycle time 50ns  Read time 25  s  Program time 200  s / page  Erase time 2ms / block  Technology 0.13  m p-sub CMOS triple-well 1poly, 1polycide, 1W, 2Al  Cell size 0.077  m2  Chip size 125.2mm2  Organization 2112 x 8b x 64 page x 1k block  Power supply 2.7V-3.6V  Cycle time 50ns  Read time 25  s  Program time 200  s / page  Erase time 2ms / block From [Nakamura02]

112. © Digital Integrated Circuits 2nd Memories Semiconductor Memory Trends (up to the 90’s) Memory Size as a function of time: x 4 every three years

113. © Digital Integrated Circuits 2nd Memories Semiconductor Memory Trends (updated) From [Itoh01]

114. © Digital Integrated Circuits 2nd Memories Trends in Memory Cell Area From [Itoh01]

115. © Digital Integrated Circuits 2nd Memories Semiconductor Memory Trends Technology feature size for different SRAM generations