1 CS612 Algorithms for Electronic Design Automation CS 612 – Lecture 1 Course Overview Mustafa Ozdal Computer Engineering Department, Bilkent University.

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1 CS612 Algorithms for Electronic Design Automation CS 612 – Lecture 1 Course Overview Mustafa Ozdal Computer Engineering Department, Bilkent University Mustafa Ozdal

2 CS 612 – Lecture 1 Mustafa Ozdal Computer Engineering Department, Bilkent University What is EDA?  Stands for Electronic Design Automation  a.k.a VLSI CAD  Software tools to support engineers in the creation of new IC designs.  EDA tools significantly reduce the cost and time-to- market of new projects.  A CPU can easily contain > 1B transistors in a single chip  Manual design is prohibitive

3 CS 612 – Lecture 1 Mustafa Ozdal Computer Engineering Department, Bilkent University What is EDA?  Solves a wide-range of problems high-level system design to fabrication (and everything in between)  Strong software skills required  This course will cover the physical design problems  Abstract and algorithmic problems  No EE knowledge needed

4 CS 612 – Lecture 1 Mustafa Ozdal Computer Engineering Department, Bilkent University Why Study EDA Algorithms?  You may consider a career in the EDA field  EDA companies: Synopsys, Cadence, Mentor Graphics, …  Design companies: Intel, IBM, Apple, AMD, Nvidia, TI, Qualcomm, ARM, TSMC, …  You may be working in a related field  e.g. Computer architecture: What is the hardware cost, energy cost, etc. of a new feature?  e.g. Scientific computing: Common algorithms used in both domains (e.g. graph partitioning, clustering, etc.)  You may want to improve your algorithmic skills  We will study algorithms for abstract problems that also occur in other domains. e.g. routing, rectangle packing, partitioning, etc.

5 CS 612 – Lecture 1 Mustafa Ozdal Computer Engineering Department, Bilkent University Course Overview  Schedule: Lecture: Tue. 13:40-14:30 EA502 Lecture: Thu. 15:40-17:30EA502 Spare Hour: Tue. 14:40:15:30  Course project: More in-depth study of a topic  Literature survey + implementation + experiments  Presentation (survey + plans)  Final report (implementation + experiments + conclusions)

6 CS 612 – Lecture 1 Mustafa Ozdal Computer Engineering Department, Bilkent University Sneak Preview of the Problems

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 2: Netlist and System Partitioning © KLMH Lienig 7 Circuit: Partitioning Problem Partition the netlist into 2 equal parts (i.e. each part must have 4 gates) such that the # of edges between two partitions is minimized.

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 2: Netlist and System Partitioning © KLMH Lienig 8 Circuit: Cut c a : four external connections Cut c a Cut c b Block ABlock B Block ABlock B Cut c b : two external connections Partitioning Problem How to do this for > 1M gates?

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 2: Netlist and System Partitioning © KLMH Lienig 9 Floorplanning Problem Example Given: Three blocks with the following potential widths and heights Block A: w = 1, h = 4 or w = 4, h = 1 or w = 2, h = 2 Block B: w = 1, h = 2 or w = 2, h = 1 Block C: w = 1, h = 3 or w = 3, h = 1 Task: Floorplan with minimum total area enclosed A A A B B C C A B C 4 3

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 2: Netlist and System Partitioning © KLMH Lienig 10 Floorplanning Problem Example Given: Three blocks with the following potential widths and heights Block A: w = 1, h = 4 or w = 4, h = 1 or w = 2, h = 2 Block B: w = 1, h = 2 or w = 2, h = 1 Block C: w = 1, h = 3 or w = 3, h = 1 Task: Floorplan with minimum total area enclosed

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 2: Netlist and System Partitioning © KLMH Lienig 11 Floorplanning Problem Solution: Aspect ratios Block A with w = 2, h = 2; Block B with w = 2, h = 1; Block C with w = 1, h = 3 This floorplan has a global bounding box with minimum possible area (9 square units). Example Given: Three blocks with the following potential widths and heights Block A: w = 1, h = 4 or w = 4, h = 1 or w = 2, h = 2 Block B: w = 1, h = 2 or w = 2, h = 1 Block C: w = 1, h = 3 or w = 3, h = 1 Task: Floorplan with minimum total area enclosed How to do this for 1000s of blocks?

Placement A C B D E F BDF ACE ACB EDF Which is better? More wirelength Harder routing Less wirelength Easier routing

Placement as an Optimization Problem Place all cells in the netlist such that: Minimize chip area Minimize wire length Make routing easy Satisfy timing constraints Keep cells on critical paths closer Satisfy various other design constraints A typical design can have > 1M cells NP-complete problem

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 5: Global Routing © KLMH Lienig © 2011 Springer Verlag 14 C D A B Netlist: N 1 = {C 4, D 6, B 3 } N 2 = {D 4, B 4, C 1, A 4 } N 3 = {C 2, D 5 } N 4 = {B 1, A 1, C 3 } Technology Information (Design Rules) Placement result Routing Problem

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 5: Global Routing © KLMH Lienig © 2011 Springer Verlag 15 Netlist: N 1 = {C 4, D 6, B 3 } N 2 = {D 4, B 4, C 1, A 4 } N 3 = {C 2, D 5 } N 4 = {B 1, A 1, C 3 } Technology Information (Design Rules) Routing Problem C D A B N1N1

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 5: Global Routing © KLMH Lienig © 2011 Springer Verlag 16 Netlist: N 1 = {C 4, D 6, B 3 } N 2 = {D 4, B 4, C 1, A 4 } N 3 = {C 2, D 5 } N 4 = {B 1, A 1, C 3 } Technology Information (Design Rules) Routing Problem C D A B N2N2 N3N3 N4N4 N1N1 How to do this for > 1M nets?