Lecture 11 ALU and Control Unit Design Presented By Dr. Shazzad Hosain Asst. Prof. EECS, NSU

Hardwired Control Design Eight Steps to follow

Step 1: Derive the Flow Chart Start Stop R  0 M  Multiplicand via inbus Q  Multiplier via inbus R  R + M Q  Q – 1 Q=0 Outbus  R no yes

Step 2: Obtain register transfer description

Step 3: Specify processing hardware along with various components

Step 4: Complete the design of the processing section M LCDLCD C 0 : R ← 0 C 1 : M ← inbus C 2 : Q ← inbus C 3 : F ← r + l C 4 : Q ← Q – 1 C 5 : outbus ← R C 6 : R ← F R CLDCLD Q LDCLDC 4 4 C0C bit adder F C1C1 C2C2 C3C3 C4C4 C5C5 C6C6 Z inbus outbus

Step 5: Determine the block diagram of the controller

Step 6: Obtain the state diagram of the controller T0T0 T1T1 T2T2 T3T3 T4T4 T5T5 Z=1 Z=0 State Diagram

Step 7: Specify the characteristics of the hardware for generating the required timing signals T0T0 T1T1 T2T2 T3T3 T4T4 T5T5 Z=1 Z=0 State Diagram

Step 7: Specify the characteristics of the hardware for generating the required timing signals T0T0 T1T1 T2T2 T3T3 T4T4 T5T5 Z=1 Z=0 State Diagram

Step 7: Specify the characteristics of the hardware for generating the required timing signals T0T0 T1T1 T2T2 T3T3 T4T4 T5T5 Z=1 Z=0 State Diagram

Step 8: Draw the logic circuit of the controller Reset 1 3 – to – 8 Decoder T0T1T2T3T4T5T0T1T2T3T4T5 unused C 0, C 1 C 2 C 3, C 4, C 6 C 5 Sequence Controller (SC) Enable Clear Load Clock O2O2 O1O1 O0O0 d 2 d 1 d 0 L Z Logic Diagram of the unsigned multiplier controller

Sequence Controller Design T3T5T3T5 InputsOutputs ZT3T3 T5T5 Ld2d2 d1d1 d0d0 0 1 x1 0 x x Truth Table _ L = Z T 3 + T 5 d 2 = T 5 _ d 1 = Z T 3 d 0 = T 5

SC Alternative Design InputsOutputs ZT3T3 T5T5 Ld2d2 d1d1 d0d0 0 1 x1 0 x x Truth Table Z T3 T5 _ L = Z T 3 + T 5 d 2 = T 5 _ d 1 = Z T 3 d 0 = T 5 L d2d2 d1d1 d0d0

Micro-programmed Control Unit Design Micro-programmed control unit contains programs written using microinstructions The programs written in ROM inside the CPU The microprocessor reads each micro-instruction into instruction register from external memory The control unit translates the micro-instructions for the microprocessor

Micro-instruction format All micro-instructions have two fields – Control word Indicates which control lines are to be activated – Next address Specifies the address of the next instruction to be executed

Design Decisions Cost of CPU depends on size of control memory Size depends on length of micro-instructions Major design decision is to reduce the length of micro-instructions Length depends on two factors – Degree of parallelism: number of microinstructions that can be activated simultaneously i.e. control bits – The method by which the address of next micro- instruction is determined

Control Bit Organization Several ways to organize – Assign a single bit for each control line, unencoded format Allows full parallelism No decoding is necessary – Assign n number of bits for 2 n number of micro instructions, encoded format Decoding is necessary Less parallelism

Unencoded vs. Encoded Format C 0 : outbus  X C 1 : outbus  Y 1.Each operation can be performed one at a time, because there is a one outbus 2.A single can be assigned for each transfer Unencoded format Two operations are performed Encoded format Three operations can be performed

Unencoded vs. Encoded Format Cont. If there are eight (8) different operations then 8 different control bits Ins. Number C0C0 C1C1 C2C2 C3C3 C4C4 C5C5 C6C6 C7C7 Operation Performed outbus  X outbus  Y ***************** X  outbus Ins. Number d2d2 d1d1 d0d0 Operation Performed 1000outbus  X 2001outbus  Y ************ 8111X  outbus Unencoded format Encoded format Horizontal microinstruction Vertical microinstruction

Designing Micro-instructions

Control Memory (CM) 6 x Condition Select Branch Adder Control Functions C 0 C 1 ……… C Micro-program Counter (MPC) Reset Load/increment MUX Z Vcc CWR (Control Word Register)

Components Micro-program Counter (MPC) – Holds the address of the next micro-instruction Control Word Register (CWR) – Contain three fields Condition select Branch address Control function MUX (Multiplexer)

References Chapter 7, Fundamental of Digital Logic and Microcomputer Design – by M. Rafiquzzaman