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Lecture 10 ALU and Control Unit Design Presented By Dr. Shazzad Hosain Asst. Prof. EECS, NSU.

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Presentation on theme: "Lecture 10 ALU and Control Unit Design Presented By Dr. Shazzad Hosain Asst. Prof. EECS, NSU."— Presentation transcript:

1 Lecture 10 ALU and Control Unit Design Presented By Dr. Shazzad Hosain Asst. Prof. EECS, NSU

2 ALU Design Arithmetic Unit Logic Unit 4-bit parallel adder C in C out x3x2x1x0x3x2x1x0 y3y2y1y0y3y2y1y0 X Y Arithmetic Unit F f3f2f1f0f3f2f1f0 A3A2A1A0A3A2A1A0 B3B2B1B0B3B2B1B0

3 Lets take the following two operations F = X + Y F = X – Y 4-bit parallel adder C in C out X F Y S001S001 = X + Y + 0 = X + (-Y) = X + (Y + 1) = X + Y + 1 4-bit parallel adder MUX 0101 0101 0101 0101 C in C out x3x2x1x0x3x2x1x0 y3y2y1y0y3y2y1y0 S0S0 F f3f2f1f0f3f2f1f0

4 Block Diagram of Arithmetic Unit Arithmetic Unit 4 4 X Y 4 F S0S0

5 Logic Unit S0S0 Operation 0X AND Y 1X XOR Y

6 Block Diagram of Logic Unit Logic Unit 4 4 X Y 4 G S0S0

7 Block Diagram of ALU Logic Unit 4 4 X Y 4 G S0S0 Arithmetic Unit 4 4 X Y 4 F S0S0 4 Multiplexer 4 Z S1S1

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10 Design of the Control Unit Two types of control unit design – Hardwired Control Design – Micro-programmed Control Unit Design

11 Basic Concepts Transfer to Transfer 14 th bit of to 1 st bit of Transfer to if E is enabled

12 Multiplication Using Addition Microprocessor speed depends on bus architecture

13 Bus Architecture Three types of bus architectures – Single-bus architecture – Two-bus architecture – Three-bus architecture

14 Single Bus Architecture

15 Two-bus Architecture

16 One of the main task of control unit is to sequence a set of operations properly Use a ring counter to implement this Timing Signals

17 Hardwired Control Design Eight Steps to follow

18 Step 1: Derive the Flow Chart Start Stop R  0 M  Multiplicand via inbus Q  Multiplier via inbus R  R + M Q  Q – 1 Q=0 Outbus  R no yes

19 Step 2: Obtain register transfer description

20 Step 3: Specify processing hardware along with various components

21 Step 4: Complete the design of the processing section M LCDLCD C 0 : R ← 0 C 1 : M ← inbus C 2 : Q ← inbus C 3 : F ← r + l C 4 : Q ← Q – 1 C 5 : outbus ← R C 6 : R ← F R CLDCLD Q LDCLDC 4 4 C0C0 44 4-bit adder F C1C1 C2C2 C3C3 C4C4 C5C5 C6C6 Z

22 Step 5: Determine the block diagram of the controller 01234560123456

23 References Chapter 7, Fundamental of Digital Logic and Microcomputer Design – by M. Rafiquzzaman


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