Objectives Understand the design environment and flow Learn how to run CADENCE tool Learn how to manage your design Learn how to create your schematic design Learn how to run simulation (HSPICE) Learn how to create your layout design Learn how to do design verification (DRC & LVS) Hierarchical design

(MOSFET, BJT, Diodes, etc.) Design Flow Schematic Design Device models (MOSFET, BJT, Diodes, etc.) Netlist Circuit Simulation (HSPICE) Layout Design Technology File DRC & LVS

Command Interpreter Window (CIW) Starting the tool icfb - all features are available layoutPlus - layout editor, DRC and LVS layout - layout editor only icms - schematic design only Menu banner Output field Input field Mouse button cues

Library Manager Tools > Library manager (in CIW) Library Cell View Create new library, cell or view Copy library, cell or view Delete library, cell or view Library Top name of your project Cell Blocks consist in your project View Properties of cell (layout, schematic, etc.)

Create A New Library File > New > Library (in LM) Type in your library name Type in your library path

Create A New Schematic CellView File > New > Cell View Composer - Schematic: Schematic design editor Composer - Symbol: Symbolic design editor Virtuoso: Layout design editor Type in cell name Choose the type of cell (view name)

Schematic Editor - Overview Check and save Save Zoom in Zoom out Stretch Copy Delete Undo Property Component Wire(Narrow) Wire(Wide) Wire name Pin Command Option Repete Mouse button cues

Add Component Modify direction Array instances

Wire & Pin Left click the start terminal and left click the end terminal You can change the routing method by right button click Fanout-4 node causes the warning message Pin name Pin type

Change Properties Only current All selected All * You can choose multiple instances by pressing the shift key Component property filed

Create Symbol Design > Create CellView > From CellView

Customizing Your Symbol Line Drawing Box Drawing Selection Box

Netlist Generation Tools > Simulation > Other (in Composer) Simulation > Initialize (in Composer) Choose run directory Simulation > Options (in Composer)

Netlist Generation (2) Simulation > Netlist/Simulate (in Composer) Choose HSPICE Uncheck simulate

Netlist File $**************************************************************************** $ HSPICE Netlist: $ $ Block: inv $ Netlist Time: Sep 26 23:28:06 1999 $ GLOBAL Net Declarations .global gnd vdd $ MODEL Declarations .model nmos nmos level=2 vto=0.7 gamma=0.2 kp=3e-05 lambda=0.02 tox=6e-07 .model pmos pmos level=2 vto=-0.7 gamma=0.4 kp=1.5e-05 lambda=0.03 tox=6e-07 $ Main Circuit Netlist: $ Last Time Saved: Sep 26 23:23:17 1999 mxp0 vdd in out vdd p w=5u l=0.8u mxn0 out in gnd gnd n w=2u l=0.8u Delete

Create Simulation Files * First line must be remark .inc your_netlist .lib your_library .option post * stimuli or signal sources vxx node1 node2 type ... ixx node1 node2 type ... * simulation cards .dc .tran .ac * do not forget me .end hspice sample.spi  Run awaves (graphical result viewer) Load the following results sample.tr# (transient results) sample.ac# (ac analysis results) sample.sw# (dc analysis results) sample.spi

Create A New Layout Design Create A New CellView with ‘Virtuoso’ Layer Select Window (LSW) Save Fit Zoom in Zoom out Stretch Copy Move Delete Undo Property Instance Path Polygon Label Rectangle Ruler

Attach Technology Library Technology File > Attach (in CIW) Your Library Technology library to be attached Check the LSW after technology file attachment

Drawing Rectangle Stretch Select layer Click start corner and click end corner Stretch Select the outline to be stretched and click Click end point

... ... Drawing Copy and Move Select layer(s) by click and drag Orthogonal Diagonal Any angle Horizontal Vertical ... Copy to Array ... select Horizontal pitch place Vertical pitch

Drawing Path (Signal Routing) Pin (terminal) Select layer first Name here Same as schematic pin type

Layer Select Window (LSW) NV - All Visible select a layer to be left click AV refresh design window AV - All Visible NS - Not Selectable select a layer to be selected all other layer will not be selected AS - All Selectable Individual layer can be ‘NS’ by right click Individual ‘NV’ layer can be visible by left click

Customizing Your Environment Design > Options > Display

Customizing Your Environment Design > Options > Editor