1. First contact with Cadence icfb
Schematics & Layout
First contact with Cadence icfb

2. Pre-Steps for windows user:
1. Get an account on the Cadence server.
2. Login into the server with ssh.
ssh
3. Start the VNC server for yourself.
vncserver –depth 24 –geometry 1024x768
Set a your vncserver password.
Remember your password and port number
4. Run VNC viewer
Server: :5901 (w/ your port)

3. Pre-Steps for windows user:
You need to re-do step 2 & 3 only after
you killed the vncserver
Or, a reboot of the server.
If you are in a network outside our lab, please contact us to get the server ip and port.

5. Pre-Steps for Linux & Mac user:
1. Get an account on the Cadence server.
2. Login into the server with ssh in any GUI.
ssh -X
You are ready to configure and run Cadence.

6. First contact
Make a directory where you want to begin and save your design.
mkdir mydesign
Change to the directory.
cd mydesign
Run cadence
csh
source (something?)
virtuoso & (virtuoso -64 if you want to run 64bit version)
Read and close the “What’s new” window.
Ready to work?

7. First contact: Ready to work?
For design safety:
You may want to mount a net drive as your design folder
Configure the PDK.
The PDK has been install on the server
You need configure your environment to invoke it.

8. Configure / invoke the PDK
Copy and rename cdsinit to your home folder
mv cdsinit .cdsinit
Copy cshrc_wrkDir and cds.lib to your design folder
cd to your design folder and run
csh
source cshrc_wrkDir
virtuoso &
You may need to update cshrc_wrkDir if you change a PDK.

9. This log window is useful.
You will know when to read it carefully.
Tools->Library Manager… is another important window. We face to it almost everyday.
You can manage (create / add/ remove) your library in this window.
Try to know more about it.
Now, this is a default library list.

10. Tools & Software for windows user
Putty.exe -- ssh tools.
vnc-4_1_3-x86_win32_viewer.exe -- vncviewer
X-windows directly on your windows desktop.
In PuTTY: Configuration->Connection->SSH-> X11->Check Enable X11 forwarding
Install Xming setup.exe, Xming-mesa setup.exe, Xming-fonts setup.exe
Start Xming
Start icfb from your ssh command line.
WinSCP
A file transfer between your PC and system server

11. To our business – schematic and layout

12. Design Flow

13. Create your library In Library manager:
File->New->Library
Name->OK
Technology File for New … ->Attach to an existing techfile->OK
Attach Design Library to Technology File smic13mmrf_1233->OK

14. Create your cell (1) In Library manager:
Select “mystudy”
File->New->Cell View
Name -> OK
In Virtuoso?Schematic Editing: mystudy…
Creat->Instance…(i)
Add Instance: Browse
Library: smic13mmrf_1233, Cell: n12, View:symbol->Close

15. Create your cell (2) Adjust parameters as needed. Hide->
Left click to place the component
ESC key to finish the placement.
Then, add a p12.
Add->Pin… p
A: input
Y: output
vcc, gnd: inputOutput

16. Create your cell (3) Add->Wire (narrow) w Save(the left check icon)
Click and connect the components.
Save(the left check icon)
The warnings are highlighted.
Modify and save again.
(No 4 wires junction, please)

17. Create a symbol for a cell view
In Schematic Editing window,
Design->Create Cellview->From Cellview OK
Symbol Generation Options
Adjust the pin location
In symbol Editing:
Change the shape with Add->Shape
Save

18. ACHTUNG!!!!WARNING!!!
Please note that usually according to normal design flow you would move onto to schematic simulation to verify that your design is correct( i.e.. Transistor sizing etc).
However, in an effort to get the student more familiar with the tools we will continue straight to layout.

19. Create your layout (1) In Library Manger window,
File->New->Library->Cell View…
Tools: layout OK
LSW window show the layer and colors
In Layout Editing windows:
Creat->Instance i
Browse and fine layout of n12 and p12

20. Create your layout (2) Press “shift+f” to switch to the detail view
Press “ctrl+f” to switch back
Click a component to select it.
Then press “q” to edit properties.

21. Create your layout (3) In Edit Instance Properties windows, In LSW
Parameter->Bodytie Type: Integrated ->Left Tap OK
In LSW
Select GT drw
In Layout Editing:
Create Path p to connect poly.
Then, connect Y w/ MET1 drw.

22. Create your layout (4) Add pin labels for each pin.
pin labels must in metal tex layers for smic130
LSW->M1TXT drw
In Layout Editing:
Create Label l (lower-case L)
Place on metal
Then,
Y, vcc, gnd

23. Design Rules Checks (DRC)
In Layout Editing:
Calibre->Run DRC
Calibre Interactive -DRC
Cancel the “Load Runset File”
Rules->Calibre-DRC Rules File->…
/eda/smic13mmrf_1233….v2.6/Calibr/DRC/SmicDR19… drc
Rules->Calibre-DRC Run Directory->…
/home/ftliang/mydesign/drc
Run DRC
Only Metal Density check can be failed during the components design.

24. Layout Versus Schematic (LVS)
In Layout Editing:
Calibre->Run LVS
Calibre Interactive –LVS
Cancel
Rules->Calibre-LVS Rules File->…
/eda/smic13mmrf….v2.6/Calibre/LVS/SmicSPM7…V2.6_ 2P.lvs_XRC
Rules->Calibre-DRC Run Directory->…
/home/ftliang/mydesign/lvs
Inputs->Netlist->Check Export from schematic …

25. Thanks & Please re-try some yourself.

26. DC simulation of a single transistor
Schematic simulation
DC simulation of a single transistor

27. Clarifications: nMOS vs pMOS
nMOS with p-substrate, pMOS w/ n-well or n-substrate

28. Clarifications: nMOS vs. pMOS
Current arrow also on the source, and current direction decides the type of MOS
Be aware of the difference between VDS and VSD

29. Outlines
What is a IV curve of a nMOS or pMOS?
Simulation test bench

30. What is a IV curve?

31. Simulation test bench 1 Start virtuoso & New cell view (schematic)
Add nMOS.
Add gnd, vdc x2 from analogLib
Connect them

32. Simulation test bench 2 Change parameters of V0, V1 with key q V0 V1
DC voltage: Vds V1
DC voltage: Vgs
Check and Save

33. Simulation Settings 1 In Virtuoso Schematic window In ADE window
Tools->Analog Environment (ADE)
In ADE window
Setup->Model Libraries & Temperature (at least)
Variables->Copy From Cellview
Edit->Vgs=0, Vds=3.3
Analyses->Choose

34. DC Simulation Settings
Choosing Analyses dc
Component Parameter
Select Component->V0->vdc->OK
Sweep Range->Start-Stop->0~1.2 OK
ADE
Outputs->To Be Plotted->Pick up the drain of nMOD

35. Setting Vgs via Parametric Analysis
ADE->Tools->Parametric Analysis…
Sweep->Parametric Set
Variable Name: Vgs
Value List:
Check Select
Analysis->Start
Nothing output?
You should “Netlist and run” first.

36. You should know How to plot schematic
How to plot simulation graph output
How to save simulation setting
How to adjust the graphs.
How to measure something on graphs.
How to calculate values in ADE and calculator.

37. Now swith Vgs and Vds
dc->V1 (Vgs)
Sweep->Vds

38. Try pMOS yourselves

39. Thanks & Please re-try some yourself.

40. Post-layout simulation
Transient simulations of a invertor
Pre- and Post-layout

41. Outlines CMOS fabrication Invertor Transient simulations Schematic
Layout
Transient simulations
Pre-layout simulation
PEX, parameter extraction
Post-layout simulation
Post-layout simulation

42. CMOS fabrication
Post-layout simulation

43. Invertor You should have your schematic and layout from Lab 1.
If you didn’t, you are fine to drop this course.
No matter your layout is good or not, it should pass the DRC and LVS.
Post-layout simulation

44. Transient simulations
Test bench
The configuration of vpulse
Why I used three invertors?
ADE
Variables->Copy FromCellview
Analyses->Choose->tran->stop time ->conservative (What is the difference?)
Output->To Be Plotted
Netlist and Run
Post-layout simulation

45. PEX, parameter extraction
Layout->Calibre->Run PEX
Ruels:/eda/smic13mmrf….v2.6/Calibre/LVS/SmicS PM7…V2.6_2P.lvs_XRC
Inputs: Netlist->Export from schematic viewer
Outputs: Netlist->Format:CALIBREVIEW, Use Names From: SCHEMATIC
Run PEX (You may get errors, let’s talk.)
Calibre View Setup window pop up.
Reset Properties: m=1 ng=1 mult=1 OK
Map calibre device
Post-layout simulation

46. Post-layout simulation
In your test bench cell
File->New->Cell View->Type: config.
Configuration
View:Schematic
Use Template…
spectre
right-click on “inverter” ->Set Cell View->calibre
Save and Close
Re-open config View
ADE
Post-layout simulation

47. Thanks & Please re-try some yourself.

48. Run group of simulations in command line.
Ocean scripts & misc.
Run group of simulations in command line.

49. Outlines Misc. Ocean script Structure of your design folders cds.lib
Copy or backup your real design
Ocean script
What is ?
Where to begin with?
Customisation
Ocean scripts

50. Structure of your design folders
Ocean scripts

51. cds.lib -- 行注释符 INCLUDE /pdk/chrt35/cds.lib
DEFINE mystudy /home/ftliang/mydesign/mystudy
In /pdk/chrt35/cds.lib
$CDSHOME/share/cdssetup/dfII/cds.lib
DEFINE chrt35dg_SiGe ./chrt35dg_SiGe
Ocean scripts

52. Copy or backup your real design
Backup: archive all your design folder.
For whole project backup, you may also backup the related pdk library.
Restore:
Modify the cds.lib DEFINE line
In virtuoso, when you make a copy, it is usually not a full backup.
Especially, it is a top level schematic or layout.
Ocean scripts

53. Ocean scripts ADE->Session->Save Ocean Script…
Edit the script as necessary.
In command line
ocean
load “xxx.ocn”
Ocean scripts

54. Thanks & Please re-try some yourself.