Field Programmable Port Extender (FPX) 1 Modular Design Techniques for the FPX

Field Programmable Port Extender (FPX) 2 Overview Motivation RAD Logic Resources RAD Infrastructure Modules –Reconfiguration Control –SRAM Interface –Control Cell Processor RAD Module Interface Top Level RAD Design –Pins and layout overview –Module instantiation

Field Programmable Port Extender (FPX) 3 Motivation for Modular Design Definitions –Modules: entities that perform network data processing FPX Applications: packet classification, compression, etc. –Infrastructure: all other entities necessary for system functionality Memory interfaces, control cell processor, reconfiguration control, etc. Assume most applications do not need all available logic and memory resources Higher performance and flexibility are achievable via multiple modules Standard module interface –Ensures module interoperability –Reduces design redundancy –Shortens module design cycle

Field Programmable Port Extender (FPX) 4 Dynamic Hardware Plugins (DHP) Programmable router with software and reconfigurable hardware packet processing Hardware plugins –Static interfaces for I/O and off- chip memory –User defined on-chip memory Infrastructure –IOC Slotted ring interface –Application Controller Reconfiguration control –Memory Interfaces SRAM/SDRAM interfaces Applications –Position independent –Dynamically loadable Prototype with WUGS/SPC/FPX –Partially reconfigure RAD FPGA for new applications

Field Programmable Port Extender (FPX) 5 RAD FPGA Logic Resources Virtex 1000E –7 FPGA 4 Global Clock Trees –(2) 100MHz clocks from FPX board Globally accessible IOBs –Versa-Ring routing –3 flops for tri-state bussing 64 x 96 CLB array –2 flops/LUTs per Slice –2 Slices per CLB –Total = 24,576 flops/LUTs 96 Block SelectRAMs –4096 bits per block –6 columns of 16 blocks –6 columns of dedicated interconnect –Total = 393,216 bits

Field Programmable Port Extender (FPX) 6 Reconfiguration Control Module Partial reconfiguration controller for RAD FPGA Executes reconfiguration handshake with NID FPGA and RAD modules Module interface –Localized synchronous reset –Enable –Ready

Field Programmable Port Extender (FPX) 7 SRAM Interface Module Interface to off-chip ZBT SRAM Abstracts modules from device specific timing Independent interface for each module Arbitrates requests and issues grant to winning module Modules retain access by holding request high after receiving grant –Modules responsible for preventing starvation

Field Programmable Port Extender (FPX) 8 Control Cell Processor Captures control cells for off- chip memory transactions –SRAM read/write –SDRAM read/write Not yet implemented Checks for correct HEC VPI = 0x000 VCI = 0x0023 (35) –Modifiable register ModuleID = 0x00 OpCodes –Even OpCodes for command cells –Response OpCode = 1+OpCode –OpCodes 0x00 to 0x0F reserved for common operations Updates CRC for response cells

Field Programmable Port Extender (FPX) 9 RAD Module Interface Cell I/O and Flow Control –32-bit wide UTOPIA-style interface w/ unique timing Off-chip Memory Access –Arbitrated access to SRAM and SDRAM via standard interface Control (clock, reset, and reconfiguration control)

Field Programmable Port Extender (FPX) 10 Control Interface 100MHz global clock (CLK) –All I/O signals should be synchronous to CLK Synchronous reset (RESET_L) –Asserted low for 1 clock cycle Reconfiguration handshake (ENABLE_L, READY_L) –Enable asserted low at reset –Module must pull READY_L high after reset, prior to accepting cells in order to prevent reconfiguration during operation –Enable asserted high prior to reconfiguration –Module stops accepting cells, flushes internal pipelines, and asserts READY_L for at least one clock cycle

Field Programmable Port Extender (FPX) 11 Cell Input Interface Start of Cell (SOC_MOD_IN) –Signals the first word of the ATM cell 32-bit wide data path (D_MOD_IN) –ATM cells transferred as (14) 32-bit words –First word arrives with SOC_MOD_IN –Remaining 13 words arrive on subsequent clock cycles Transmit Cell Available (TCA_MOD_IN) –Signals module’s ability to accept a cell –Must be valid 6 clock cycles prior to the last cycle of the current cell transfer

Field Programmable Port Extender (FPX) 12 Cell Output Interface Start of Cell (SOC_OUT_MOD) –Signals the first word of the ATM cell 32-bit wide data path (D_OUT_MOD) –ATM cells transferred as (14) 32-bit words –First word sent with SOC_MOD_IN –Remaining 13 words sent on subsequent clock cycles Transmit Cell Available (TCA_OUT_MOD) –Signals output’s ability to accept a cell –Modules must sample TCA_OUT_MOD no sooner than 3 clock cycles prior to asserting SOC_OUT_MOD

Field Programmable Port Extender (FPX) 13 SRAM Interface Arbitration Handshake –SRAM_REQ requests and holds memory access –SRAM_GR grants access and initiates access termination –Module may retain memory access for duration of transaction set If grant is de-asserted, module must complete current transaction and release memory Module is responsible for preventing starvation Reads –Hold SRAM_RW high, issue address –Data appears inside module 6 clock cycles later Writes –Assert SRAM_RW low, issue address and data –Data will be written 5 clock cycles later IMPORTANT: HOLD SRAM_RW HIGH TO PREVENT OVERWRITING VALID MEMORY DATA

Field Programmable Port Extender (FPX) 14 SRAM Interface Timing All I/O signals must be flopped at module boundary to ensure timing constraints are met Timing diagrams take reference point from inside module and assume boundary flops

Field Programmable Port Extender (FPX) 15 RAD FPGA (Chip View) RAD Pin Mappings Ingress Path (LC) –Input SOC_LC_NID D_LC_NID TCAFF_LC_RAD –Output SOC_LC_RAD D_LC_RAD TCAFF_LC_NID Egress Path (SW) –Input SOC_SW_NID D_SW_NID TCAFF_SW_RAD –Output SOC_SW_RAD D_SW_RAD TCAFF_SW_NID SRAM Interfaces SDRAM Interfaces SDRAM2 InputOutput Egress Path (SW) InputOutput Ingress Path (LC) SDRAM1 SRAM2 SRAM1

Field Programmable Port Extender (FPX) 16 Design Issues & Recommendations Keep routing delays in mind during initial design phase, use conservative estimates Conform to the Module Interface Specification Use provided infrastructure Flop all module I/O signals –Position independent modules Use synchronous reset Perform cell I/O simulations Experiment with synthesis and PAR options –Over-constrain timing delays –Significant deviations in timing results occur with various options, including hierarchy ungrouping and routing algorithms Share experience and wisdom with other developers