1. Department of Computer Science and Engineering
D. Lakshmi
Assistant Professor
Department of Computer Science and Engineering
Bannari Amman Institute of Tech
Sathyamangalam
15/12/2007

2. Introduction to DMA
Allows external devices to access memory without processor intervention
Requires a DMA control circuit which is part of I/O device interface called DMA Controller.
To transfer the data between external devices and memory the following instructions :
Move DATAIN R0 [ From External Device to Memory]
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3. Steps a DMA Device Interface Must Take to Transfer a Block of Data
Become bus master
Send memory address and R/W signal
Synchronized sending and receiving of data using Complete signal.
4. Synchronization is achieved through Interrupt Enable Flag and Interrupt Request Flag.
5. Release bus as needed (perhaps after each transfer).
6. Advance memory address to point to next data Item.
7. Count number of items transferred and check for end of data block.
8. Repeat if more data to be transferred.
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4. Steps a DMA Device Interface Must Take to Transfer a Block of Data
Many DMA Controllers can be used. Among different DMA devices, top priority is given to high-speed peripherals such as a disk, a high-speed network interface or a graphics display device.
Two types of DMA interweaving techniques
Cycle stealing – DMA device takes the memory from the processor and steals the one cycle required for read or write.
Block or Burst Mode – DMA controller may be given exclusive access to the main memory to transfer a block of data without interruption.
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5. Bus Arbitration
Bus Master: The device that is allowed to initiate data transfers on the bus at any given time is called bus master.
Bus Arbitration: It’s the process by which the next device to become the bus master is selected and bus mastership is transferred to it.
Centralized Arbitration: A single bus arbiter performs the required arbitration.
Distributed Arbitration: All devices participate in the selection of the next bus master.
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6. Centralized Arbitration
1. Bus Request Line – A wired ‘OR’ that the controller knows a request was made, but does not know which device made the request.
2. Bus Grant Line – First a signal is propagated to all devices. The Bus Grant Line is asserted to the first device in the chain. If that device made the request it takes a hold of the bus and leaves the Bus Grant Line negated for the next device in the chain. If that device didn’t make the request then the Bus Grant Line is asserted for the next device in the chain.
If two devices make a request for the bus at the same time then the device closer to the controller gets the bus. This is called daisy chaining
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7. Centralized Arbitration – Using Daisy Chaining
DMA Controller sends Bus-Request to become bus master
Processor activates Bus-Grant signal, BG1, indicating to the DMA controllers that they may use the bus when it becomes free.
Bus master indicates to all other devices by activating BBSY that it is using the bus
BBSY
Processor BR
DMA
Controller 1
DMA
Controller 2
BG1
BG2
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8. Distributed Arbitration
Start-Arbitration Signal: When one or more devices request the bus, hey assert this signal
Open Collector lines ARB0 – ARB3: 4-bit ID number is placed on these lines
A winner is selected as a result of the interaction among the signals trnsmited over these lines.
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9. Synchronous data transmission Asynchronous data transmission
Buses
The bus lines used for transferring data may be grouped into three types: data address, and control lines (R/W). And also it carries timing information-they specify the times at which the processor and the I/O devices may place data on the bus or receive data from the bus.
The device that initiates data transfer is called an initiator (master).
The device addressed by the master is referred to as a slave or target.
Synchronous data transmission
Asynchronous data transmission
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10. All devices derive timing information from a common clock line.
Synchronous Bus
All devices derive timing information from a common clock line.
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11. Sequence of signals during transfer of bus mastership
At time t0, the master places the device address on the address lines and sends an appropriate command on the control lines.
At time t1, addressed device responds and it places the requested input data on the data lines.
At time t2, the master strobes the data on the data lines into its input buffer.
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12. Multiple Cycle transfers
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13. Asynchronous Bus
Data transfer is done based on he use of handshake signal between he master and the slave.
The common clock is replaced by two timing control lines, Master Ready and Slave ready.
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14. Parallel Port Keyboard to processor connection
Data
Encode
and
Debouncing
Circuit
Keyboard
Swithes
Processor
DATAIN
Address
Data
R/W
SIN .
Master-ready
Valid
Input Interface
Slave-ready
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15. Printer to Processor connection
Data
Processor
Printer
DATAIN
Address
Data
R/W
SOUT
Valid
Master-ready
Idle
Ouput Interface
Slave-ready
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16. A serial interface Serial Input Input shift register My address
Chip and
register select
RS1
RS0
DATAIN
R/W
Ready …
Accept D7 D0
DATAOUT
Serial Output
Output shift register
Status and control
Receiving clock
INTR
Transmission clock
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17. Computer system using different interface
Main memory
Processor
Processor Bus
Bridge
PCI Bus
Additional Memory
SCSI controller
Ethernet interface
USB controller
ISA interface
SCSI bus
Video
IDE disk
Disk Controller
CD ROM controller
Disk1
Disk2
CD ROM
Keyboard
Game
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18. PCI bus in a computer system
Host
Main memory
PCI bridge
PCI bus
Disk
Printer
Ethernet interface
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19. Data transfer signals on the PCI bus
Name Function
CLK A 33-MHz
FRAME# Sent cy the initiator to indicate the duration of a transaction
AD address/data lines, which may be optionally increased to 64
C/BE# command/byte-enable lines
IRDY#,TRDY# Initiator-ready and target-ready signals
DEVSEL# A response from the device indicating that it has recognized its address and is ready for a data transfer transaction
IDSEL# Initialization Device Select
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20. SCSI
Memory
disk
CPU
SCSI
Ethernet
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