1 4 PCB: LEFT TOP 115 channels, LEFT BOTTOM (115), RIGHT TOP (106), RIGHT BOTTOM (106). For LEFT TOP board 115 channels we have: 115 smd connectors (AMP.

Slides:

Advertisements

Similar presentations

SQUARE PAD PCB DESIGN Elizabeth Starling, Jerry Collins Florida Institute of Technology High Energy Physics Lab A January 26 th, 2015.

Advertisements

Rosier Ph. – IPNO – Detector Dpt. – 27/05/2011APRIME HPS collaboration meeting 1/24 1- Vacuum chamber proposal 1.1- Stainless steel chamber design and.

Ecal Connection board and Motherboard design. Connection Board Motherboard.

STURM2 Motherboard Jussi Malin. STURM2 motherboard  Board dimensions 10,9 X 12 inches  8 electrical layers  Houses 192 amplifiers, 8 daughter cards,

Endcap Muon meeting: UC Davis, Feb , 2005 J. Hauser UCLA 1 TMB and RAT Status Report Outline: Current status of TMB and RAT boards Noise measurements.

CMS WeekDec 2002E. Hazen HF Electronics Status Report E. Hazen, J. Rohlf, E. Machado Boston University.

1 Module and stave interconnect Rev. sept. 29/08.

Coldfire Computer Final Presentation Josh Hudgins Randy Jedlicka Drew Larson Project Staff:

Printed Circuit Board Design

Mauro Raggi Status report on the new charged hodoscope for P326 Mauro Raggi for the HODO working group Perugia – Firenze 07/09/2005.

LSU 06/04/2007Electronics 81 CAD Tools for Circuit Design Electronics Unit – Lecture 8 Schematic Diagram Drawing Etched Circuit Board Layout Circuit Simulation.

STATUS OF THE CRESCENT FLEX- TAPES FOR THE ATLAS PIXEL DISKS G. Sidiropoulos 1.

Chamber PCB s, FEB s, Cooling, HV/LV Distribution 1)PCB designs-track widths, track to track distances … 2) Double sided and Multi layer, modular approach.

Panda PCB for prototype status report by D Malkevich on behalf of the ITEP group ITEP.

VELO upgrade electronics – HYBRIDS Tony Smith University of Liverpool.

The printed circuit board (PCB) design

PCB layout issues PCB alignment and spacing MMM meeting, 22/01/2014G. Sekhniaidze/ J. Wotschack1.

WP7&8 Progress Report ITS Plenary meeting, 23 April 2014 LG, PK, VM, JR Objectives 2014 and current status.

CMS ECAL End Cap EDR Meeting CERN 28 Nov. to 29 Nov 2000 A.B.Lodge - RAL 1 ECAL End Cap CMS ECAL End Cap Engineering Design Review. EDR meeting held 28.

1 HV Bias Power Patch Panel for Scintillator KLM Gerard Visser Xiaowen Shi overview Schematics layout Parts.

“CAE-CAD-CAM” TECHNIQUES FOR DEVELOPMENT OF ELECTRONIC MODULES Faculty of Electronics and Information Technology University “Politehnica” of Bucharest.

Current ILC work at Fermilab Electrical Engineering Dept.

Dimensions of the PDM frame: 167mm x 167mm x 28.7mm.

CVD PCB, first steps. 15 mm 25 mm Chip area. No ground plane underneath the chip. Bulk isolated => only one ground line Power lines Connector: 11,1mm*2,1mm:

1 Module and stave interconnect Rev. sept. 29/08.

1 E906 Pre-Amplifier Card 2009/10/07. 2 E906 Wire Chambers Station1 MWPC: –build a new E906 MWPC. –4500 channels in total. Station2 DC: –recycle old E866.

EC front unit status. Outline Conclusions from mechanical prototype and actions taken Status of electrical prototype KIT’s work for TA Dev plan (tests)

General Purposes Input/ Output Daughter board for Univ Eval Rev B Julien Cercillieux University of Hawaii

Figure 1: ICD Single Channel Block Diagram Schematic PMT High Voltage Supply (see Figure 4 & 4a) LED Pulser PMT Calibration (see Figure 6) ICD Scintillator.

CMS ECAL End Cap Meeting CERN 19 June to 23 June 2000 A.B.Lodge - RAL 1 ECAL End Cap High Voltage Cards and 2000 Electrical/Thermal Model. Progress on.

Tariq J. Solaija, NCP Forward RPC EDR, Tariq Solaija Forward RPC EDR The Standard RPC for low  regions Tariq J. Solaija National Centre for.

HV connection for a Common GEM foil design Aiwu Zhang

High Speed Interconnect Solutions HIROSE ELECTRIC IT3-32mm SI Report Three-Piece Mezzanine Connector for 20+ Gbps Applications October 29, 2009.

1 PreFPIX2 Inner board and test beam triggering Gabriele Chiodini Fermilab - Jan 07, 02.

EC_ASIC drawing (1) ASIC BASIC FASIC D 68 pi ns ASIC A 68 pi ns ASIC C ASIC E 120 pins ABCDEF 68 pi ns 68 pi ns 68 pi ns 68 pi ns.

Trace connecting two pads! More than 45 degree bends Traces too close together Rule of thumb: traces at least 40 mil apart.

HCAL – Integration Plans Mathias ReineckeHCAL – Main meeting Introduction 2.HCAL Base Unit (HBU) - Update 3.Testboards 4.Light Calibration System.

TCSP Presentation #3 Team 14 SPOT DASH. Schematics 3 Pages 3 Pages Page 1: Buttons, LEDs, sensors related circuits Page 1: Buttons, LEDs, sensors related.

Givi Sekhniaidze1 CERN, 25 March Givi Sekhniaidze2 The angles for the chambers are: LM1 – ° LM2 – 7.224° SM1 – ° SM2 – ° Do we.

E-Cal Readout Boards - 8 Boards total -Design & Fabrication at Jlab - Assembly at Orsay Nick Nganga HPS Collaboration Oct Jlab.

The HULK Luke Johnston Ethan Byler Dhruv Lamba Andy Robison.

Forward Calorimeter Baseplane and FC1 Layer Sum Board D. Tompkins 30 June 2015.

Front End Board (16 channels) Superlayer Cross Section Frontend Enclosure HV cap board HV cap Board Signals from chamber wires go to HV cap board to be.

Vessel dimensions GTK assembly carrier Electrical connections Cooling pipes integration Vessel alignment with the beam Next steps Conclusion 3/10/20102.

End-of-stave region. 2 Space Z-dimension is critical –Keep gap small (might help getting rid of stubs) Edge of last barrel silicon (at corner) is 1277.

TRIO-CINEMA 1 UCB, 2/08/2010 CINEMA Solar Array Design Review Yashraj Khaitan David Glaser Kevin Jenkins Chris Pasma Space Sciences Laboratory University.

1 LAPPD Team meeting 6/10/2010 Ossy Siegmund, Experimental Astrophysics Group, Space Sciences Laboratory, U. California at Berkeley Integration of Front-End.

Saverio MINUTOLIElectronics WG - 09 June AFEC cross-talk Plots illustrating Cross-talk effect AFEC pcb investigation.

PHENIX Safety Review Overview of the PHENIX Hadron Blind Detector Craig Woody BNL September 15, 2005.

Belle-II iTOP HVB Status SLIDE FOR INCLUSION IN GARY’S PRESENTATION Belle II General Meeting Gerard Visser Indiana University CEEM 11/13/2012.

The printed circuit board (PCB) design §PCB design is part of the design process of a product in electronics industry. §PCB is a piece of insulating plastic.

WP7&8 Progress Report ITS Plenary meeting, 10 June 2014 LG, PK, VM, JR.

Electronics for CEDAR Cristina Lazzeroni, Marian Krivda, Richard Staley, Xen Serghi, Karim Massri University of Birmingham, UK 3/5/

CCB to OH Interface M.Matveev Rice University February 22,

Drift Chamber Review Jefferson Lab 6-8 March 2007 CLAS12 Drift Chamber Electronics R. Chris Cuevas Group Leader -- Fast Electronics Jefferson Lab Physics.

T HE PDM INTEGRATION P. Barrillon (LAL) & G. Prévôt (APC) On behalf of the PDM crew (Simon, Lech, Philippe, Sylvie B) EUSO-SPB/MiniEUSO progress meeting,

Outline Upgrade status of the ECAL/HCAL HV control mezzanine board;  Firmware design,  Setup for making functional tests and validation FPGA firmware.

2 March 2012Mauro Citterio - SVT Phone meeting1 Peripheral Electronics Some updates Mauro Citterio INFN Milano.

Test beam straw prototype production status

Calorimeter Mu2e Development electronics Front-end Review

High-Speed Serial Link Layout Recommendations –

ob-fpc: Flexible printed circuits for the alice tracker

Development electronics SIPM-MU2e

HPS Motherboard Electronic Design

Some proposals on HV circuits realization for segmented straw detector

First of all we will remind some numbers:

Electronics for the E-CAL physics prototype

University of Wisconsin-Madison / SSEC

Assembly order PCB design

Outer Endcap External Bus tape

Presentation transcript:

1 4 PCB: LEFT TOP 115 channels, LEFT BOTTOM (115), RIGHT TOP (106), RIGHT BOTTOM (106). For LEFT TOP board 115 channels we have: 115 smd connectors (AMP 10 pin) for preamp very similar to previous version (pin slightly smaller). It is the same of FT- Cal motherboard. 15 TE signal connectors from 16 pin each, equal to previous version. 2 HV connectors (15 pin) DSUB 750V, 5A, trough hole different to previous for a easier routing. 1 LV connectors (6 pin). We can use a very similar HV grouping. We can use the same cable as discussed with Stepan Stepanyan. HPS Motherboard Electronic Design

2 Design Block of 10

3 LEFT TOP Design (115 channels)

4 LEFT BOTTOM Design (115 channels)

5 HV Grouping (Proposal)

6 LEFT TOP Mechanical (from Orsay)

7 4 PCB: LEFT TOP 115 channels, LEFT BOTTOM (115), RIGHT TOP (106), RIGHT BOTTOM (106). Board Dimension is 400x240 mm and 143 component each. Board Thickness = 2.5 mm. Layout specifications: 10 Layers (3 signals + 1 for High Voltage + 1 fan-out + 5 GND). 115 signal traces with 50 Ohms impedance. Signal: 0.2 mm line width and 0.2 mm min. spacing. HV: 0.5 mm line width and 0.8 mm min. spacing. Ground ring between two signals. HPS Motherboard Layout Design

8 LEFT TOP Routing (preliminary)

9 Routing Zoom on 3 columns

10 Mechanical Specifications with Orsay. Done! Design of LEFT TOP and LEFT BOTTOM boards. Done! Layout routing of LEFT TOP and LEFT BOTTOM boards. NOW Design of RIGHT TOP and RIGHT BOTTOM boards with the correct HV grouping. November. Layout routing of RIGHT TOP and RIGHT BOTTOM boards. End of year. Board Productions and Assembly (with the same company used for the FT-Cal). rough estimate 5Keuro. January Test on Electrical connections and Full crosstalk test with FT-Cal crystals. February HPS Motherboard Next Steps