EE2174: Digital Logic and Lab Professor Shiyan Hu Department of Electrical and Computer Engineering Michigan Technological University CHAPTER 8 Arithmetic

1-Dec-15 PJF - 2Arithmetic Overview Binary Addition Binary Addition Complement forms Complement forms Subtraction Subtraction Multiplication Multiplication

Objectives of This Lecture What have we learned? What have we learned? Combinational Circuit Basics Combinational Circuit Basics Three Design Methodologies Three Design Methodologies What are we going to learn? What are we going to learn? Applying the above knowledge to design Adder Applying the above knowledge to design Adder This is the most fundamental arithmetic module design This is the most fundamental arithmetic module design 1-Dec-15 PJF - 3Arithmetic

1-Dec-15 PJF - 4Arithmetic 1-bit Addison Performs the addition of two binary bits. Performs the addition of two binary bits. Four possible operations: Four possible operations: 0+0=0 0+0=0 0+1=1 0+1=1 1+0=1 1+0=1 1+1=10 1+1=10 Circuit implementation requires 2 outputs, one to indicate the sum and the other to indicate carry. Circuit implementation requires 2 outputs, one to indicate the sum and the other to indicate carry.

1-Dec-15 PJF - 5Arithmetic Half Adder: Definition A half adder is to perform a 1-bit addition. A half adder is to perform a 1-bit addition. Inputs: A 0, B 0 Inputs: A 0, B 0 Outputs: S 0, C 1 Outputs: S 0, C 1 Index indicates significance, 0 is for LSB and 1 is for the next higher significant bit. Index indicates significance, 0 is for LSB and 1 is for the next higher significant bit. Boolean equations: Boolean equations: S 0 = A 0  B 0 S 0 = A 0  B 0 C 1 = A 0 B 0 C 1 = A 0 B 0 A0A0A0A0 B0B0B0B0 S0S0S0S0 C1C1C1C Truth Table

1-Dec-15 PJF - 6Arithmetic Half Adder: Implementation S 0 = A 0  B 0 S 0 = A 0  B 0 C 1 = A 0 B 0 C 1 = A 0 B 0 The output of a half adder are AND and XOR results of the two given input bits. The output of a half adder are AND and XOR results of the two given input bits. A0A0A0A0 B0B0B0B0 S0S0S0S0 C1C1C1C1 Logic Diagram 1 bit half adder A0A0A0A0 B0B0B0B0 C1C1C1C1 S0S0S0S0 Block Diagram

1-Dec-15 PJF - 7Arithmetic n-bit Addition Design an n-bit binary adder which performs the addition of two n-bit binary numbers and generates a n-bit sum and a carry out. Design an n-bit binary adder which performs the addition of two n-bit binary numbers and generates a n-bit sum and a carry out. Example: Let n=4 C out C 3 C 2 C 1 C A 3 A 2 A 1 A B 3 B 2 B 1 B S 3 S 2 S 1 S Example: Let n=4 C out C 3 C 2 C 1 C A 3 A 2 A 1 A B 3 B 2 B 1 B S 3 S 2 S 1 S

1-Dec-15 PJF - 8Arithmetic Full Adder: Definition In a half adder, only two input bits are considered. In a half adder, only two input bits are considered. What if there is a carry from the less significant bits? What if there is a carry from the less significant bits? A full adder is to perform the additions of 3 bits, i.e., two input bits and a carry- in bit. A full adder is to perform the additions of 3 bits, i.e., two input bits and a carry- in bit.

1-Dec-15 PJF - 9Arithmetic Full Adder: Implementation (1) AiAiAiAi BiBiBiBi CiCiCiCi SiSiSiSi C i The K-maps for The K-maps for C i+1 : C i+1 : S i : S i : BiCiBiCiBiCiBiCi AiAiAiAi BiCiBiCiBiCiBiCi AiAiAiAi

1-Dec-15 PJF - 10Arithmetic Full Adder: Implementation (2) Boolean equations: Boolean equations: C i+1 = A i B i + A i C i + B i C i C i+1 = A i B i + A i C i + B i C i S i = A i B i ’ C i ’ + A i ’B i ’C i + A i ’B i C i ’ + A i B i C i = A i  B i  C i S i = A i B i ’ C i ’ + A i ’B i ’C i + A i ’B i C i ’ + A i B i C i = A i  B i  C i You can design a full adder directly from the above equations (requires 3 ANDs and 1 OR for C i+1 and 2 XORs for S i ) You can design a full adder directly from the above equations (requires 3 ANDs and 1 OR for C i+1 and 2 XORs for S i ) Can we do better? Can we do better?

1-Dec-15 PJF - 11Arithmetic Observations Derivation Derivation C i+1 = A i B i + A i B i ’C i + A i ’B i C i C i+1 = A i B i + A i B i ’C i + A i ’B i C i = A i B i + (A i B i ’ + A i ’B i )C i = A i B i + (A i  B i )C i and S i = A i  B i  C i and S i = A i  B i  C i Why it helps? Why it helps? We can first compute AND and XOR results among A i and B i, i.e., A i B i and A i  B i, using a half adder. We can first compute AND and XOR results among A i and B i, i.e., A i B i and A i  B i, using a half adder. Let D i =A i  B i. Let D i =A i  B i. Next we can compute D i C i and D i  C i using the other half adder. Next we can compute D i C i and D i  C i using the other half adder.

Full Adder by 2 Half Adders A full adder can be implemented using two half adders and an OR gate. A full adder can be implemented using two half adders and an OR gate. 1-Dec-15 PJF - 12Arithmetic 1-Dec-15 PJF - 12Arithmetic AiAiAiAi BiBiBiBi CiCiCiCi C i+1 SiSiSiSi 1 bit full adder AiAiAiAi BiBiBiBi C i+1 SiSiSiSi CiCiCiCi

Exercise 1 How many gates are reduced by the half adder based implementation? How many gates are reduced by the half adder based implementation? How many transistors are needed in the half adder based implementation? How many transistors are needed in the half adder based implementation? See page 35 in chapter 4 See page 35 in chapter 4 34 transistors 34 transistors 1-Dec-15 PJF - 13Arithmetic

1-Dec-15 PJF - 14Arithmetic n-bit Combinational Adders Perform multi-bit addition Perform multi-bit addition How? How?

1-Dec-15 PJF - 15Arithmetic n-bit Ripple Carry Adder It is constructed using n 1-bit full adder blocks. It is constructed using n 1-bit full adder blocks. Cascade the full adders so that the carry out from one becomes the carry in to the next higher bit position. Cascade the full adders so that the carry out from one becomes the carry in to the next higher bit position.

1-Dec-15 PJF - 16Arithmetic Example: 4-bit Ripple Carry Adder C 4 C3 C2 C1 C0 A3 A2 A1 A0 +B3 B2 B1 B S3 S2 S1 S0 C 4 C3 C2 C1 C0 A3 A2 A1 A0 +B3 B2 B1 B S3 S2 S1 S0

Characteristics of Ripple Carry Adder Simple design Simple design What is the limitation? What is the limitation? 1-Dec-15 PJF - 17Arithmetic

1-Dec-15 PJF - 18Arithmetic Ripple Carry Adder Delay Circuit delay in an n-bit ripple carry adder is determined by the delay on the carry path from the LSB (C 0 ) to the MSB (C n ). Circuit delay in an n-bit ripple carry adder is determined by the delay on the carry path from the LSB (C 0 ) to the MSB (C n ). Let the delay in a 1-bit FA be . The delay of an n-bit ripple carry adder is n  since it is a sequential computation. Let the delay in a 1-bit FA be . The delay of an n-bit ripple carry adder is n  since it is a sequential computation.

Exercise 2 What could be a potential improvement in terms of delay? What could be a potential improvement in terms of delay? Suppose that two 128-bit numbers are to be added. Suppose that two 128-bit numbers are to be added. 1-Dec-15 PJF - 19Arithmetic 128 bits A 127,…………………………….…., A 0 B 127,……………………………..…., B 0

Main Idea: Predict Carry In Use three 64-bit adders Use three 64-bit adders One computes the lower 64 bits, one computes higher 64 bits assuming the carry in C 64 is 0, and one computes higher 64 bits assuming the carry in C 64 is 1. One computes the lower 64 bits, one computes higher 64 bits assuming the carry in C 64 is 0, and one computes higher 64 bits assuming the carry in C 64 is 1. All three adders compute simultaneously All three adders compute simultaneously After that, one knows the right carry in C 64. After that, one knows the right carry in C 64. One just needs to pick the correct result corresponding to the right C 64. One just needs to pick the correct result corresponding to the right C Dec-15 PJF - 20Arithmetic 64 bits A 127,………., A 64 B 127,………., B 64 A 63,………., A 0 B 63,………., B 0 C 64 =0 64 bits A 127,………., A 64 B 127,………., B 64 C 64 =1

Advantage and Limitation What is the delay? What is the delay? 64  for each adder 64  for each adder Assuming that picking time is also , total delay is 65 . Assuming that picking time is also , total delay is 65 . What is the limitation? What is the limitation? To add two n-bit numbers, what is the best delay? To add two n-bit numbers, what is the best delay? Implementation? Implementation? 1-Dec-15 PJF - 21Arithmetic

Summary of This Lecture A half adder adds 2 input bits but not the carry in bit. A half adder adds 2 input bits but not the carry in bit. A full adder adds 2 input bits and the carry in bit. A full adder adds 2 input bits and the carry in bit. A fully adder can be efficiently implemented using 2 half adders and an OR gate. A fully adder can be efficiently implemented using 2 half adders and an OR gate. A ripple carry adder consists of n full adder sequentially to perform n bit addition. A ripple carry adder consists of n full adder sequentially to perform n bit addition. It is simple but with significant delay which needs improvement. It is simple but with significant delay which needs improvement. 1-Dec-15 PJF - 22Arithmetic

1-Dec-15 PJF - 23Arithmetic Decimal Arithmetic Design circuits that perform decimal arithmetic such as addition and multiplication. Design circuits that perform decimal arithmetic such as addition and multiplication. Input is in binary coded form in BCD Input is in binary coded form in BCD BCD Decimal Adder BCD Decimal Adder 4 bits per decimal number as input 4 bits per decimal number as input 5 bits as output indicate the decimal sum and the carry 5 bits as output indicate the decimal sum and the carry Remember BCD addition rules. Remember BCD addition rules. Add 0110 to the sum if it is greater than or equal to 1010 Add 0110 to the sum if it is greater than or equal to 1010 That is, 1010, 1011, 1100, 1101, 1110, 1111 That is, 1010, 1011, 1100, 1101, 1110, 1111

1-Dec-15 PJF - 24Arithmetic Binary Coded Decimal (BCD) Adder Addend 4-bit binary adder z3 z2 z1 z0 4-bit binary adder S3 S2 S1 S0 BCD sum 0 K C C = K + z3z2 + z3z1

1-Dec-15 PJF - 25Arithmetic 2’s Complement For a positive n digit number N 2 in binary, the 2's complement, 2C(N 2 ), is given by: For a positive n digit number N 2 in binary, the 2's complement, 2C(N 2 ), is given by: 2C(N 2 ) = 2 n -N 2, if n > 0 0, if n = 0 2C(N 2 ) = 2 n -N 2, if n > 0 0, if n = 0 Example: N 2 =1010 Example: N 2 =1010 2C(N 2 ) = 2 4 -N 2 = – = C(N 2 ) = 2 4 -N 2 = – = Example: N 2 =11111 Example: N 2 = C(N 2 ) = 2 5 -N 2 = – = C(N 2 ) = 2 5 -N 2 = – = {

1-Dec-15 PJF - 26Arithmetic 2’s Complement (cont.) Here’s an easier way to compute the 2’s complement: Here’s an easier way to compute the 2’s complement: 1. Leave all least significant 0’s and first 1 unchanged. 2. Replace 0 with 1 and 1 with 0 in all remaining higher significant bits. Examples: Examples: N = 1010 N = N = 1010 N =

1-Dec-15 PJF - 27Arithmetic 1’s Complement For a positive n digit number N 2 in binary, the 1's complement, 1C(N 2 ), is given by: For a positive n digit number N 2 in binary, the 1's complement, 1C(N 2 ), is given by: 1C(N 2 ) = (2 n -1) - N 2 1C(N 2 ) = (2 n -1) - N 2 Example: N 2 =011 Example: N 2 =011 1C(N 2 ) = (2 3 -1)-N 2 = – = C(N 2 ) = (2 3 -1)-N 2 = – = Example: N 2 =1010 Example: N 2 =1010 1C(N 2 ) = (2 4 -1) - N 2 = – = C(N 2 ) = (2 4 -1) - N 2 = – = Observation: 1’s complement can be derived by just complementing all the bits in the number. Observation: 1’s complement can be derived by just complementing all the bits in the number.

1-Dec-15 PJF - 28Arithmetic Observation Compare 1’s complement with 2’s complement: Compare 1’s complement with 2’s complement: 2 n -N = [(2 n -1) - N] n -N = [(2 n -1) - N] + 1 Thus, the 2’s complement can be obtained by deriving the 1’s complement and adding 1 to it. Thus, the 2’s complement can be obtained by deriving the 1’s complement and adding 1 to it. Example: Example: N = 1001 N = C(N) = 2 4 – N = – 1001 = C(N) = 2 4 – N = – 1001 = C(N) = 2 4 – 1 - N = 1111 – 1001 = C(N) = 2 4 – 1 - N = 1111 – 1001 = 0110  2C(N) = 1C(N) + 1 = = 0111

1-Dec-15 PJF - 29Arithmetic Subtraction with 2’s complement A-B can be simply computed as A+2C(B) and deleting the leading the carry 1 A-B can be simply computed as A+2C(B) and deleting the leading the carry (111)-(011)=(111)+(101)=(1100) (111)-(011)=(111)+(101)=(1100) delete the carry which gives (100) delete the carry which gives (100)

1-Dec-15 PJF - 30Arithmetic Subtraction with 1’s complement A-B can be simply computed as A+1C(B), deleting the carry and adding 1 A-B can be simply computed as A+1C(B), deleting the carry and adding (111)-(011)=(111)+(100)=(1011) (111)-(011)=(111)+(100)=(1011) Delete carry which gives (011) Delete carry which gives (011) Add 1 which gives (100) Add 1 which gives (100)

1-Dec-15 PJF - 31Arithmetic Binary Adder/Subtractors If we perform subtraction using complements, we eliminate subtraction operation, and thus, can use an adder with appropriate complementer for subtraction. If we perform subtraction using complements, we eliminate subtraction operation, and thus, can use an adder with appropriate complementer for subtraction. Thus, to form an adder-subtractor circuit, we only need a selective complementer and an adder. Thus, to form an adder-subtractor circuit, we only need a selective complementer and an adder. The subtraction A-B can be performed by taking the 2's complement of B and adding to A. The subtraction A-B can be performed by taking the 2's complement of B and adding to A. The 2's complement of B can be obtained by complementing B and adding one to the result. A-B = A + 2C(B) = A + 1C(B) + 1 = A + B’ + 1 The 2's complement of B can be obtained by complementing B and adding one to the result. A-B = A + 2C(B) = A + 1C(B) + 1 = A + B’ + 1

1-Dec-15 PJF - 32Arithmetic 4-bit Binary Adder/Subtractor – XOR gates act as programmable inverters

1-Dec-15 PJF - 33Arithmetic When S=0, the circuit performs A + B. The carry in is 0, and the XOR gates simply pass B untouched. When S=0, the circuit performs A + B. The carry in is 0, and the XOR gates simply pass B untouched. Assume that A > B. When S=1, the carry into the least significant bit (LSB) is 1, and B is complemented (1’s complement) prior to the addition; hence, the circuit adds to A the 1’s complement of B plus 1 (from the carry into the LSB). Assume that A > B. When S=1, the carry into the least significant bit (LSB) is 1, and B is complemented (1’s complement) prior to the addition; hence, the circuit adds to A the 1’s complement of B plus 1 (from the carry into the LSB). 4-bit Binary Adder/Subtractor (cont.)

1-Dec-15 PJF - 34Arithmetic 4-bit Binary Adder/Subtractor (cont.) S=0 0 B0B0 S=0 selects addition B1B1 B2B2 B3B3

1-Dec-15 PJF - 35Arithmetic 4-bit Binary Adder/Subtractor (cont.) S=1 1 B0’B0’ S=1 selects subtraction B1’B1’B2’B2’B3’B3’

1-Dec-15 PJF - 36Arithmetic Binary Multiplier Binary multiplication resembles decimal multiplication: Binary multiplication resembles decimal multiplication: n-bit multiplicand is multiplied by each bit of the m-bit multiplier, starting from LSB, to form n partial products. n-bit multiplicand is multiplied by each bit of the m-bit multiplier, starting from LSB, to form n partial products. Each successive set of partial products is shifted 1 bit to the left. Each successive set of partial products is shifted 1 bit to the left. Derive result by addition the m rows of partial products. Derive result by addition the m rows of partial products.

1-Dec-15 PJF - 37Arithmetic Half Adders are Sufficient since there is no Carry-in in addition to the two inputs to sum Binary Multiplier Circuit 2-bit by 2-bit multiplier

1-Dec-15 PJF - 38Arithmetic Summary Binary Addition Binary Addition Complement forms Complement forms Subtraction Subtraction Multiplication Multiplication