16th April 2008R. Bates Glasgow University Experience with an industrial vendor in the manufacture of 3D detectors R. Bates, C. Fleta, D. Pennicard, C. Parkes University of Glasgow N. Tartoni, J. Marchal, Diamond Synchrotron

R. Bates Glasgow University 16th April 2008 Outline 3D detector Processes required  Leads to identification of supplier Process flow at IceMOS  One way to make a 3D detector  Some process optimisation Devices designed Problem we had  Detail of the problem  Consequences Some nice results New process flow Future work

R. Bates Glasgow University 16th April D detectors Maximum drift and depletion distance governed by electrode spacing  Lower depletion voltages  Radiation hardness  Fast response  Active edges: same technology dope edges of sensor for edgeless detection efficiency  At the price of more complex processing  Narrow dead regions at wells Proposed by Parker, Kenney 1995 Unit cell defined by e.g. hexagonal array of electrodes Planar Device3D Device Stanford

R. Bates Glasgow University 16th April 2008 Wafer bonding WAFER BONDING (mechanical stability) Si-OH + HO-Si -> Si-O-Si + H 2 O DEEP REACTIVE ION ETCHING (electrodes definition) Bosch process SiF 4 (gas) +C 4 F 8 (teflon) IR picture of 2 bonded wafers 3D detector: processing 260µm 15µm 13µm Aspect ratio up to 25:1 Depends on processor IceMOS Tech Ltd Deep reactive ion etching

R. Bates Glasgow University 16th April D detector: processing D d LOW PRESSURE CHEMICAL VAPOR DEPOSITION (Electrodes filling with conformal doped polysilicon) 2P 2 O 5 +5 Si-> 4P + 5 SiO 2 2B 2 O 3 +3Si -> 4 B +3 SiO 2 METAL DEPOSITION Shorting electrodes of the same type with Al for strip electronics readout or deposit metal for bump-bonding n p+p+ 2.9  m TEOS Poly Junction 10  m n p+p+ CNM Barcelona Polysilicon contactOpening in the passivation P-type Hole Metal Stanford ATLAS pixel design Hole filling Metal deposition

R. Bates Glasgow University 16th April 2008 Identification of supplier Non-standard detector processing stages  Wafer bonding  Deep etching  Deep poly filling  Planarization (optional) RD50 two institutes involved  CNM – no Wafer Bonding, full hole process  FBK – no Wafer Bonding, hole etch to come Stanford  Research lab with full capabilities Sintef  use Stanford poly filling IceMOS  Wafer Bonding, hole etching, planarization (CMP), poly process  Not a detector fabricator!

R. Bates Glasgow University 16th April 2008 IceMOS Technology Ltd, Belfast Leading supplier of:  Thick film bonded SOI (Silicon On Insulator) wafers.  Trench etch and refill technology  Dielectrically isolated substrate preparation New process: Through- wafer interconnect technology Through wafer via in 430um thick 150mm wafer Excellent planarity on top surface no topology

First process flow at IceMOS 1.n-type Silicon, 500μm, 4inch wafer 2.Oxidation, pattern with resist for n- holes, etch oxide 3. ICP etching (~250μm), strip resist 4.Poly fill, n-dope 5. Poly planarization front and back 6. Oxidation 7. P-electrodes OUTSOURCED, (same fashion as n-type) 8. Grind/polish to expose electrodes in front and back sides 9. Field oxide (800nm) 10. Etch oxide (contacts), metal, passivation

R. Bates Glasgow University 16th April 2008 Final device, no p-stops Si-n+ poly-n+ Si-p+ poly-p+ SiO2 Passivation (1.1 um SiO2) Si(n) Al/Si 1.5um Readout in p-columns only → no p-stops Bias in n-columns All metal lines on the top surface No active edges

R. Bates Glasgow University 16th April 2008 Hole optimization. From here… (1-May) ‘Mouse-bites’ due to breakdown of the passivation on the sidewalls ‘V’ shaped vias Usually make trenches, deep narrow holes posed a development opportunity STS Machine

R. Bates Glasgow University 16th April 2008 … to here (12-Jun) Circular holes, 10um diameter Aspect ratio ~27:1 Wafers can be polished after electrode fabrication to remove widening at the top

R. Bates Glasgow University 16th April 2008 Electrode formation Poly deposition P+ dope poly (1.5h at 1000C) + Drive in to form n+ junctions Holes : partially filled with LPCVD poly doped with P and oxide removed filled with more poly annealed to drive the dopant Final device Repeat 1 &2

R. Bates Glasgow University 16th April 2008 Doping tests: Phosphorus First tests (not including B doping) B-doping outsourced  contribution NOT included Profiles too deep  Redesign of fabrication process to reduce thermal budget (halved the poly doping time to 1.5hours per layer)  (simulation) Expected final profile 4um + B doping contribution = ~6um After P doping: 5 um into the Si Final: 9 um into the Si (3+3hours P doping)

R. Bates Glasgow University 16th April 2008 Wafer design Pixel detectors 4 Medipix2  Pitch 55 μm, 256x256 6 Pilatus  Pitch 172 μm, 97x60  1, 4 or 9 cells/pixel Strip detectors 4 large (“Beetle”) strips  Pitch 80 μm, 128x small (“Hermes”) strips  Pitch 125 μm, 32x10  Square or hexagonal cell Pad detectors, test structures

R. Bates Glasgow University 16th April 2008 First production: Medipix2 Pitch 55 μm 256x256 pixels Collects electrons and holes Readout in p+ holes N+ holes shorted together and biased via a wirebond pad (not shown) 55 μm Bump

R. Bates Glasgow University 16th April 2008 Small problem : big consequences A Few test structures had larger diameter holes  Etch rate much higher  Etched all the way through wafer  Wafers broke (5/6) during CMP processing  To fragile for final p-type poly removal (polish)  To fragile therefore final support material not removed P-type poly wet etched (at Queens in a few days) not polished  Etch rate not well understood  Slight over etching Alignment marks over etched  Bad alignment of Opening in oxide for metal contact Metal traces P-holes over wet etched  Current higher than expect Low yield of devices Etch problem did not occur on “mechanical-low res” wafers which  don’t have these problems

R. Bates Glasgow University 16th April 2008 Over etching of p-holes during non-standard removal of poly N-holes OK – covered with oxide P-holes larger – wet over etching P N Over etching of alignment marks

R. Bates Glasgow University 16th April 2008 Results Over etched p-holes  Alignment problem  Excess current Some devices work okay Rectifying junctions HV stability IV and CV curves reasonable

16th April 2008 Test structures 1 (n/p) hole surrounded by 4 (p/n) holes Pitch is 80um Central hole Bias Note that the n-holes will be shorted by the e- accumulation layer on the surface. Guard ring e- layer

R. Bates Glasgow University 16th April 2008 I-V test structures : n-holes (Open symbols: guard ring) Current falls as accumulation layer depleted n-hole isolated!

R. Bates Glasgow University 16th April 2008 I-V test structures: p-holes (Open symbols: guard ring) Average current = 6nA per hole Current plateaus at 2V (  lateral depletion)

R. Bates Glasgow University 16th April 2008 I-V in strip detector No guard ring, neighbouring strips biased 1.25mm long strip of 10 holes/strip at 125um pitch 12nA/hole

R. Bates Glasgow University 16th April 2008 Depletion - single hole test structure Ave. full lateral depletion at 3.5V Resistivity 3kohm.cm (nominal 2 to 5) Full depletion (19 V) as expected from depth of holes (250um) and wafer thickness (380um)

R. Bates Glasgow University 16th April 2008 New flow Aim: Faster  Go to 6inch wafer so in factory main process flow Safer  Use support wafer so less likelihood of damage  More time spent checking alignment marks and “minor” details Better doping profile  Lower thermal budget as fewer oxidation stages Result: Full double sided processing Active edges possible (not on first run)

R. Bates Glasgow University 16th April nd flow: final device Not to scale metal oxide PECVD oxide n+, P doped poly p+, B doped poly 250um n- silicon

R. Bates Glasgow University 16th April 2008 Future work 2 nd process flow about to start  Expect devices with higher yield and fast turn around  Strip detectors : Lab and MIP Test beam  Bumpbond pixel devices (x-ray detectors: Synchrotron and lab tests ) 3 rd process flow  p-type material / n-column readout  Need p-stops to do this.  Active edges (perhaps?)

R. Bates Glasgow University 16th April 2008 Extra Slides

R. Bates Glasgow University 16th April 2008 First Process flow in detail

R. Bates Glasgow University 16th April 2008 Starting material – DSP silicon 4”

R. Bates Glasgow University 16th April 2008 oxidise

R. Bates Glasgow University 16th April 2008 Pattern n+ holes

R. Bates Glasgow University 16th April 2008 Etch oxide

R. Bates Glasgow University 16th April 2008 DRIE silicon etch – 300um

R. Bates Glasgow University 16th April 2008 Strip resist

R. Bates Glasgow University 16th April 2008 Poly deposition

R. Bates Glasgow University 16th April 2008 N+ dope poly

R. Bates Glasgow University 16th April 2008 Poly deposition

R. Bates Glasgow University 16th April 2008 Drive to form n+ junctions

R. Bates Glasgow University 16th April 2008 Planarise poly front&back Planarise oxide

R. Bates Glasgow University 16th April 2008 Oxidise to protect n+ columns

R. Bates Glasgow University 16th April 2008 Pattern p+ holes

R. Bates Glasgow University 16th April 2008 Etch oxide

R. Bates Glasgow University 16th April 2008 DRIE silicon etch ~ 300um

R. Bates Glasgow University 16th April 2008 Strip resist

R. Bates Glasgow University 16th April 2008 Poly deposition

R. Bates Glasgow University 16th April 2008 P+ dope poly

R. Bates Glasgow University 16th April 2008 Poly deposition

R. Bates Glasgow University 16th April 2008 Drive to form p+ columns Poly-p+ Si-p+

R. Bates Glasgow University 16th April 2008 Grind/polish back to expose holes on backside

R. Bates Glasgow University 16th April 2008 Planarise front side

R. Bates Glasgow University 16th April 2008 Field oxide

R. Bates Glasgow University 16th April 2008 Pattern and etch contact windows

R. Bates Glasgow University 16th April 2008 Dep metal/pattern/etch metal contacts

R. Bates Glasgow University 16th April 2008 Dep/pattern/etch passivation

R. Bates Glasgow University 16th April 2008 Final device, no p-stops Si-n+ poly-n+ Si-p+ poly-p+ SiO2 Passivation (1.1 um SiO2) Si(n) Al/Si 1.5um

R. Bates Glasgow University 16th April nd process flow in detail

R. Bates Glasgow University 16th April 2008 Grow oxide layer Starting wafer thickness approx 600 um Oxide thickness 8000 A

R. Bates Glasgow University 16th April 2008 Pattern alignment marks

R. Bates Glasgow University 16th April 2008 Etch alignment marks Etch greater than 250 um

R. Bates Glasgow University 16th April 2008 Oxide liner Oxide thickness 0.2 um

R. Bates Glasgow University 16th April 2008 Poly refill Poly must fill holes

R. Bates Glasgow University 16th April 2008 Planarise Planarise both sides

R. Bates Glasgow University 16th April 2008 N+ pattern

R. Bates Glasgow University 16th April 2008 Etch oxide (N+ holes)

R. Bates Glasgow University 16th April 2008 Etch silicon (N+ holes) Etch 250 um deep Keep profile same as 4” lot

R. Bates Glasgow University 16th April 2008 Strip PR

R. Bates Glasgow University 16th April 2008 Poly refill & phos dope 6 um of poly Ensure columns filled 2um + P diff + 2um + Pdiff + 2um

R. Bates Glasgow University 16th April 2008 Polish poly layer

R. Bates Glasgow University 16th April 2008 Join to oxidised mechanical support wafer Support wafer oxide thickness not important – used as a grind stop.

R. Bates Glasgow University 16th April 2008 Planarise poly/Strip oxide

R. Bates Glasgow University 16th April 2008 Grind & polish to expose vias

R. Bates Glasgow University 16th April 2008 Grow oxide Oxide thickness 8000 A

R. Bates Glasgow University 16th April 2008 Photo P+ holes

R. Bates Glasgow University 16th April 2008 Etch oxide

R. Bates Glasgow University 16th April 2008 Etch silicon

R. Bates Glasgow University 16th April 2008 Strip PR

R. Bates Glasgow University 16th April 2008 Poly refill & boron dope Ensure columns filled

R. Bates Glasgow University 16th April 2008 Planarise front side

R. Bates Glasgow University 16th April 2008 Grind off handle Grind stopping on oxide.

R. Bates Glasgow University 16th April 2008 Deposit metal 1.5 um Al1%Si

R. Bates Glasgow University 16th April 2008 Etch oxide

R. Bates Glasgow University 16th April 2008 Metal photo

R. Bates Glasgow University 16th April 2008 Etch metal

R. Bates Glasgow University 16th April 2008 Deposit metal on backside 1.5 um Al1%Si

R. Bates Glasgow University 16th April 2008 Deposit & pattern passivation 1.1 um PECVD SiO2

R. Bates Glasgow University 16th April 2008 (CF) Final device