Ariadne’s Thread Kristian Zarb Adami

Simulator Aims ۞ Provide the system architect a tool to visualise trade-offs in designs ۞ Provide the scientist top-level performance numbers for a given system ۞ Maintain a close relationship with the cost-model so that cost estimates can be derived from the model ۞ Maintain a close relationship with the telescope simulation environments (eg. MeqTrees) ۞ Provide an easy route to implementation

The Specification hierarchy … Line Sensitivity Continuum Sensitivity Survey Speed FoV Dynamic Range BandwidthA eff T sys Dynamic Range # of bits# of channels # of beams Front-End Analog Antenna Efficiency Digital Processing Signal Transport CORRELATION & IMAGE PIPE Cost & Functional Model Sky Science Engineering Software

Digital Aperture Array Beam Pattern showing interference cancellation

2-Pad System Example ۞ Log-Periodic Dipole Array between 0.3 – 1GHz ۞ Demonstrate All-Digital Aperture Array for beam- forming, calibration and RFI mitigation ۞ Demonstrate scalability in terms of power consumption, cost and performance ۞ Demonstrate functionality in terms of bits, bandwidth and beams... (0... One-tile sub-array antenna unit of 8x8x2 LP dipoles Main LN Amplifiers and WB Filters 63)x2 8x8x2 ADC... (063)x2 (063)x2... Frequency splitting onto 1024 subbands... (0 1023)x2... (01023)x2 Frequency splitting onto 1024 subbands 2.4GS/s 4-bit real 4-bit imag Equaliser 2.4MS/s 4-bit real 4-bit imag 1024x2 8-bit preset coefficients... Polarisation correction of each H-V pair... Polarisation correction of each H-V pair... (0 1023)x2 (0... 8x8x2 2D FFT 0 8x8x2 2D FFT (0 63)x Beam selector and beam- steering 8 Beam selector and beam- steering... (0 8)x2 FOV correction FOV correction... (0 8)x2... (0 8)x2 Analog Processing Digital Processing

Analog Model Outside Station

Digitisation ۞1 st filter response ۞Channel Selection ۞4-bit ‘Ideal’ ADC

A/D Converters ۞ 4-bit 2.4 GS/s CMOS already available at sample level ۞ Front-End bit-count can be increased to 8 (~50dB of Dynamic Range) for RFI mitigation, with reduced bit- count at the back-end ۞ Equalization ‘may’ also be included in this block ۞ Decimation and digital formatting can be integrated into back-end of A/D

Channelization ۞ Form channels from each ADC ۞ Different channelisation algorithms can be tried ۞ Equalisation can be implemented as part of the channelisation block ۞ Data is now moved to the beamformer (windowing can occur in beamforming block)

Channelization Algorithms Algorithm Decomposition into 1024 sub-bands No. of GMACs Per polarisation per element DSP Operations Direct time DecimatorFor 5-taps = 1272 GOps FFT (no-filtering)For Radix-2 = 24144GOps Polyphase + FFT5-taps FIR filter + FFT (Radix-2) 216GOps Analysis Filter Bank (Wavelets) For 10 stages = 4802,880GOps

Cost/Power Calculations for 1 st stage Total RequirementsStream XXX (register files)XXX (on-chip mem.) Chips to sustain Ops1 11 Power for Operations (FIR)1.92W Power for Operations (FFT)1.92W Chips to sustain Bandwidth2 11 Total Power required for Bandwidth3.00E-01W Chips required2.00E E+00 Power/Chip for Operations (FIR)9.60E-01W 9.60E+01 Power/Chip for Operations (FFT)9.60E-01W 9.60E+01 Power/Chip for Bandwidth1.50E-01W3.00E-01 Total Power per Chip (FIR)1.11W (FFT)1.11W Cost per Chip ($)149$100 Cost per GMAC ($)1.16$0.78 Total Power2.22W Total Cost298$100.00

۞ Side-lobes considerably reduced with increasing number of bits ۞ Trade-off number of taps with coefficient accuracy ۞ Aim to relate this with science goals Poly-phase filtering Response

FFT Beamformer ۞ Form many beams at once ۞ Different beams in different directions ۞ Windowing function can be used to suppress sidelobes (especially 13.0dB from rectangular window) ۞ Trade-off windowing with sidelobe height and A eff /Gain

8-pt FFT ۞ 8-pt FFT real-time model implementation ۞ Twiddles can be retrieved from memory ۞ Easy mapping onto FPGA/RPA interface

Fixed vs. Floating Point ۞ Bit-growth per stage ۞ 4-bit FFT vs. floating point

Windowing for Sidelobe Cancellation

Reconfigurable Processor Arrays ۞ Heterogeneous Array of Instruction cells ۞ Rate controller to control delay in data paths ۞ I/O Ports mapped as instruction cells ۞ Low Power / Area ۞ Highly Configurable ۞ High I/O Bandwidth Configuration stream Program counter Data Memory or ADC I/O Ports Program Memory Rate Control + << x

Example Code void oned_dct (int *coeff,int *block) { b0 = coeff[0]; b1 = coeff[1]; b2 = coeff[2]; b3 = coeff[3]; b4 = coeff[4]; b5 = coeff[5]; b6 = coeff[6]; b7 = coeff[7]; e = b1 * const_f7 - b7 * const_f1; f = b5 * const_f3 - b3 * const_f5; c4 = e + f; c5 = e - f; h = b7 * const_f7 + b1 * const_f1; g = b3 * const_f3 + b5 * const_f5; c6 = h - g; c7 = h + g; c0 = (b0 + b4) * const_f4; c1 = (b0 - b4) * const_f4; c2 = b2 * const_f6 - b6 * const_f2; c3 = b6 * const_f6 + b2 * const_f2; b5 = (c6 - c5) * const_f0; b6 = (c6 + c5) * const_f0; b0 = c0 + c3; b1 = c1 + c2; b2 = c1 - c2; b3 = c0 - c3; block[0] = b0 + c7; block[1] = b1 + b6; block[6] = b1 - b6; block[7] = b0 - c7; block[2] = b2 + b5; block[3] = b3 + c4; block[4] = b3 - c4; block[5] = b2 - b5; } Datapath example: Step 1 Step 2 Step 3 Step 4 Step 5 Step 6 2 ns 1 ns 4 ns 2 ns 3 ns 1 ns

RPA Solution - Datapath Illustration Step 1 Step 2 Step 3 Step 4 Step 5 Step 6 Configuration stream Program counter Data Memory or ADC I/O Ports Program Memory Rate Control + << x Off-chip bandwidth ~ 10 Gbit/s Intra-cell bandwidth ~ 100 Gbit/s

Future Work ۞ Include clock delays for each block to ensure real-time data tracking (as well as JITTER !!!) ۞ Include a calibration model for Gain/Phase each antenna ۞ Relate beam-forming to FoV to work out the trade-off between number of beams vs. no. of bits/ beam ۞ Relate DSP-induced noise to noise temperature to work out contribution to T sys ۞ Relate side-lobe suppression models to Dynamic Range and Image Fidelity ۞ Produce Cost / Power benchmarks for each block for input into the Cost Model ۞ Extend model to the full-frequency coverage of a station ۞ Produce technology and architecture roadmaps including cable architecture

Extra slides Science Goals Technology Capabilities $$ Software Capabilities Simulation s

Error Modelling ۞ Quantization error dependent on bit-width ۞ Scaling considerations are IMPORTANT