GLD Intermediate tracker task list Configuration & software Silicon Sensor Electronics Support structure H.J.Kim, Kyungpook U. for intermediate tracker group ACFA 8 workshop

Intermediate Tracker in GLD W-Si Cal TPC Beam Pipe IP IT VTX

Configuration How many layers in central part? Disk type of endcap? ( for physics & PFA) Single side vs Double side SD Background study in endcap region Simulation with different IT configuration Optimization for physics improvement IT track reconstruction and linking with VTX and tracking

GLD Default Geometry (vtx/tracking only) IT (as in gld_v1.dat and C++ codes): spatial resolution 10  m 4 layers (561  m Silicon strip) r=9 cm (innermost), 30 cm (outermost) half z = 18.5 cm (innermost), 62 cm (outermost) |cos  |<0.9 CAD drawing by S.K.Park TPC

With and W/O IT H. Ha Without IT: 3.9 x (GeV) -1 (high momentum limit) With IT: 4.4 x (GeV) -1 default goal(?): 5x10 -5 (GeV) -1 Geant4/single (cos  =0)  /p T 2 (GeV) -1 TPC only TPC+VTX TPC+IT+VTX  /p T 2 sampling term multiple scattering term TPC only10.9 x x TPC+VTX4.37 x x TPC+IT+VTX3.87 x x GeV

e+e-  ZH, ZZ Study (ongoing) m H = GeV  = 1.7 GeV Y.I.Kim ee  ZH GLD default configuration (input m H = 120 GeV + PYTHIA) ee  ZZ Fit result: We have been (and will be) working on roles of IT in terms of physics...

Z (cm)R (cm) Layer Layer Layer Layer Layer Layer Layer CAD drawing by S.K.Park/H. Park (Tesla-like version) Endcap

Silicon sensor Double side vs single side sensor Characterization of sensor and S/N DC vs AC type Pixel for the endcap near beampipe region? Radiation damage Cost issue Above issue should be cleared by R&D and simulation

512ch 50  m pitch 1x1cm 2 PIN diode 64ch 50  m pitch 16ch 50  m pitch Rear-side of SSD Pixel Array For SDD R&D 32ch 50  m pitch N-side Design

S/N of DSSD 32ch pattern Signal mean = Pedestal mean = Pedestal sigma = 15.9 S/N = 24.9

Korea Cancer Center Hospital : 35MeV proton cyclotron Radiation Hardness Test

Electronics & support structure PreAmp (+shaping and holder with VA) Hibrid board (control +HV) FADC Long ladder issue (S/N ) Material budget (multiple scattering) Above issues should be cleared by R&D

Hybrid Board Design HV Pad

Status of Hybrid Board Hybrid board was powered up (July 2) hybrid board control board (spartan3) HV/level shift/LV generator VA

Results on S/N Collaboration Paris-Prague New 20 L=28cm, S/N(MPV)=20 or S/N(Mean)=30 L=56cm, S/N(MPV)=12 or S/N(Mean)=18 Cluster size~2 Noise vs capa Next steps: Change detector & FE prototypes go to test beam

Two designs SCIPP-UCSC: Double-comparator discrimination system  Improve spatial resolution (25%) Next foundry: May 9. LPNHE-Paris: Analogue sampling+A/D, including sparsification on sums of 3 adjacent strips. Deep sub micron CMOS techno. First chip successfully submitted and now under test Next version: in progress